d239de803c
Do not rely on environment variables for any intra-project paths
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It's no longer necessary to source `sourceme` before running any
of the project Makefiles.
2024-05-27 16:53:06 +01:00
141da55507
tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about.
2024-05-27 12:24:54 +01:00
5b31e26790
tb Makefile: use clang++-16 explicitly, because clang++-18 (now default on Ubuntu 24.04) has a >20x compile time regression
2024-05-27 11:06:50 +01:00
a693cdd632
Fix up cxxrtl include paths for new yosys
2023-12-12 19:00:26 +00:00
d8cc132a49
tb_cxxrtl Makefile: make synthesis depend on config headers
2023-04-01 04:41:39 +01:00
e89ab0d095
tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ
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(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.
2023-03-31 02:11:52 +01:00
18d3b03cc8
Fix rm of build directory in tb_cxxrtl/Makefile
2023-03-30 22:43:48 +01:00
c41fe0609b
Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
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Fix a couple of minor test script issues.
2023-03-26 23:00:18 +01:00
97509f548a
tb_cxxrtl Makefile: better support for building multiple tb configurations
2023-03-24 18:44:37 +00:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
b7d9defcf2
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
2022-07-05 03:37:19 +01:00
20f06c4a02
Build tb with 4 PMP regions by default
2022-05-24 20:06:57 +01:00
ba81b533d2
Build core with U mode support for tb
2022-05-24 16:44:22 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
01d9617f9c
Add multicore tb integration file
2021-12-17 00:41:23 +00:00
f64f44f7af
Add test for identification CSRs vs expected values
2021-12-11 13:26:59 +00:00
c90727b05a
Remove padding after vector table in init.S
2021-12-11 12:22:23 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
5d2a562f65
Just use read_verilog; write_cxxrtl when building tb_cxxrtl
2021-07-22 17:30:30 +01:00
c56c75e14b
More dicking with yosys cmd for tb_cxxrtl;
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Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
2021-07-18 16:46:00 +01:00
12bf9bb570
Make CXXRTL testbench ~25% faster
2021-07-18 16:04:19 +01:00
5cc483898d
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
2021-07-10 21:02:18 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
Luke Wren
whitequark