Luke Wren
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8014239d47
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openocd tb: report AHB error response when processor accesses outside of RAM/IO
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2021-07-17 19:26:05 +01:00 |
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Luke Wren
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ab0b4a04f0
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Also support progbuf in abstractauto.
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2021-07-17 15:08:00 +01:00 |
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Luke Wren
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62822b2e1d
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Couple of usability improvements for openocd testbench
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2021-07-15 19:42:49 +01:00 |
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Luke Wren
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9643a57ba9
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Slightly less braindead TCP interactions for openocd JTAG bitbang testbench, much more interactive now
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2021-07-14 19:20:27 +01:00 |
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Luke Wren
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307955c810
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Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
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2021-07-13 01:10:55 +01:00 |
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Luke Wren
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42632e325a
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Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
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2021-07-12 21:21:16 +01:00 |
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Luke Wren
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f7b3097ad6
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Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
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2021-07-11 16:20:39 +01:00 |
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Luke Wren
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5cc483898d
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Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
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2021-07-10 21:02:18 +01:00 |
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Luke Wren
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58a6b8b4c8
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Add 32IM testlist
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2021-06-05 12:03:05 +01:00 |
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Luke Wren
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be79a611e1
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Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.
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2021-06-04 09:19:18 +01:00 |
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Luke Wren
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c03bc2efb5
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Update init.S for new IRQ functionality
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2021-06-04 08:16:54 +01:00 |
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Luke Wren
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12851d3742
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Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
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2021-05-30 19:52:46 +01:00 |
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Luke Wren
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12205f12c7
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Add instruction fetch match check
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2021-05-30 11:22:36 +01:00 |
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Luke Wren
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16dc905dce
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Add simple formal bus properties check
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2021-05-30 10:19:42 +01:00 |
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Luke Wren
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2330b84b73
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Use .f for riscv-formal tb dependencies, small reshuffling of directories
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2021-05-30 09:44:57 +01:00 |
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Luke Wren
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089bcc7c43
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Typo
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2021-05-29 23:24:18 +01:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |
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Luke Wren
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08e986912c
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Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
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2021-05-22 11:18:56 +01:00 |
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Luke Wren
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cc6f590f2e
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Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
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2021-05-22 10:16:02 +01:00 |
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Luke Wren
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692abbad8b
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Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
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2021-05-22 07:55:13 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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Luke Wren
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6dad4e20bb
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Import from hazard5 9743a1b
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2021-05-21 02:34:16 +01:00 |