Luke Wren
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81aec325bb
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ecall from U-mode has a different mcause value than ecall from M-mode
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2022-05-28 12:07:29 +01:00 |
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Luke Wren
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f2876eb51f
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Fix bad mepc reported after branching to a branch in a no-X address range
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2022-05-27 22:47:04 +01:00 |
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Luke Wren
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e208652ad7
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Fix misa value in csr_id test
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2022-05-26 00:48:12 +01:00 |
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Luke Wren
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5be8835365
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Add missing output to pmp_write_and_lock test
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2022-05-25 15:34:28 +01:00 |
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Luke Wren
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399dcf2cb9
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Add test for U-mode X permissions
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2022-05-25 13:47:16 +01:00 |
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Luke Wren
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7340765699
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Add simple test to read, write and lock PMP registers
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2022-05-25 02:05:24 +01:00 |
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Luke Wren
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456810b09e
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Make vcd generation optional in runtests
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2022-05-24 22:56:13 +01:00 |
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Luke Wren
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64d9f4a111
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Add tests for execution of mret and wfi in U mode
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2022-05-24 22:14:20 +01:00 |
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Luke Wren
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7cfc976ef2
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Set U RWX permission on all of memory in the U CSR readability test
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2022-05-24 19:58:12 +01:00 |
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Luke Wren
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f033cde874
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Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
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2022-05-24 17:30:24 +01:00 |
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Luke Wren
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0199f48087
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Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
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2022-05-24 16:44:03 +01:00 |
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Luke Wren
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ef35dc859d
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Add zicsr to march in makefiles
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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07d4b23a9a
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Add option to pass test list to runtests
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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5ab60422ad
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Add minimal multicore launch code
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2021-12-17 01:24:11 +00:00 |
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Luke Wren
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88fea7acfa
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Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
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2021-12-12 18:28:23 +00:00 |
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Luke Wren
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719c21fec3
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Add IRQ tests. Disable waves by default in runtests
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2021-12-12 15:53:04 +00:00 |
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Luke Wren
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9fb2af800f
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Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
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2021-12-12 14:58:50 +00:00 |
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Luke Wren
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a232833d81
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Add CSR writable test
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2021-12-12 14:23:34 +00:00 |
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Luke Wren
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7da67a0600
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Similarly for minstret
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2021-12-11 22:25:12 +00:00 |
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Luke Wren
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1b722b5f27
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Add mcycle test, fix incorrect description of mcycle in docs
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2021-12-11 21:21:31 +00:00 |
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Luke Wren
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93eca19aeb
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Add test for lr/sc RAW stalls
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2021-12-11 19:16:41 +00:00 |
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Luke Wren
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763a5cd364
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Add test for readability of all implemented CSRs
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2021-12-11 17:50:12 +00:00 |
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Luke Wren
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7b1da32af1
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Move expected_output into tests inline
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2021-12-11 16:58:25 +00:00 |
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Luke Wren
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9460b3cd04
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Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
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2021-12-11 15:52:34 +00:00 |
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Luke Wren
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f64f44f7af
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Add test for identification CSRs vs expected values
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2021-12-11 13:26:59 +00:00 |
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Luke Wren
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3fe0d92d41
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Add load/store alignment testcases
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2021-12-11 12:53:37 +00:00 |
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Luke Wren
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6edfbfae8b
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Add ebreak size/alignment test
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2021-12-11 11:17:24 +00:00 |
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Luke Wren
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abe1769929
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Add instruction access fault testcase
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2021-12-11 09:54:00 +00:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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fadb9601de
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Illegal instruction test
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2021-12-10 00:11:18 +00:00 |
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Luke Wren
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3d2c912b4f
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Add test script to make it easier to add software testcases
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2021-12-09 22:25:18 +00:00 |