Luke Wren
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9e11c0e5a8
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Fix tdata1.dmode being writable from M-mode
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2022-08-23 00:08:17 +01:00 |
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Luke Wren
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cd69fcdbbc
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Docs: Add date to title page, and rebuild PDF with recent CSR changes
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2022-08-08 23:57:20 +01:00 |
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Luke Wren
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026b529bc5
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Fix asm example in docs to set meicontext.clearts when saving
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2022-08-07 23:17:39 +01:00 |
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Luke Wren
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69917ccbbe
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Docs: Tweak meicontext with thoughts that came up whilst implementing it
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2022-08-07 20:31:14 +01:00 |
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Luke Wren
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054c4a6a9c
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Fix reversed pseudocode for ctz/clz
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2022-08-02 21:21:44 +01:00 |
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Luke Wren
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adf81abfdc
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Oops, description of shxadd had operands swapped
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2022-07-31 17:45:14 +01:00 |
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Luke Wren
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e76b82e447
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More thoughts about interrupts, starting to look plausible
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2022-07-31 16:16:16 +01:00 |
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Luke Wren
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106c4c3d28
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Update docs CSR section to reflect addition of U-mode, PMP etc.
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2022-07-30 21:19:30 +01:00 |
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Luke Wren
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c73c09a48a
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More thinking about interrupt priorities
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2022-07-30 15:42:26 +01:00 |
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Luke Wren
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7946432d7a
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Speculatively update docs with new interrupt array/priority stuff, and sleep register
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2022-07-28 01:18:13 +01:00 |
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Luke Wren
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ae30d7c0d2
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Add instruction pseudocode (no A extension)
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2022-07-10 19:16:43 +01:00 |
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Luke Wren
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956b386a20
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Update instruction listings in docs
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2022-07-10 05:47:19 +01:00 |
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Luke Wren
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1697192c62
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Fix cycle timing docs for sc.w: 2 cycles if next instruction is RAW-dependent.
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2021-12-12 20:50:26 +00:00 |
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Luke Wren
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8a003dbbed
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Make mcycle/minstret inhibited by default
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2021-12-12 13:55:33 +00:00 |
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Luke Wren
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7da67a0600
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Similarly for minstret
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2021-12-11 22:25:12 +00:00 |
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Luke Wren
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1b722b5f27
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Add mcycle test, fix incorrect description of mcycle in docs
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2021-12-11 21:21:31 +00:00 |
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Luke Wren
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6ef3503ef5
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Add A bit to MISA, update docs
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2021-12-07 05:10:20 +00:00 |
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Luke Wren
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9e7ea4adb6
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Fix column width
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2021-12-06 17:14:23 +00:00 |
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Luke Wren
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df658d86ff
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First plausibly working AMOs. Add AMOs to instruction timings list
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2021-12-04 23:44:22 +00:00 |
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Luke Wren
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a8933c332d
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Fix illegal issue of pipelined exclusives on the bus, and document correct timings
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2021-12-04 18:23:01 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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52ba930638
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Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
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2021-12-04 01:17:57 +00:00 |
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Luke Wren
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cd1b391714
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More docs cleanup
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2021-12-02 02:29:34 +00:00 |
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Luke Wren
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ebe87dce46
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Reorganise CSR section of docs
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2021-12-02 01:35:18 +00:00 |
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Luke Wren
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c5e85dea4c
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Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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0fafae1ab1
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Regenerate PDF
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2021-11-28 16:27:54 +00:00 |
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Luke Wren
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9bf4d5105f
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Describe possible debug topologies. Update pdf.
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2021-11-28 09:01:23 +00:00 |
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Luke Wren
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79c29354d2
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Update docs with bitmanip instructions
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2021-11-28 03:16:45 +00:00 |
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Luke Wren
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b0d11c0ab7
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Add RISC-V debug tests
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2021-07-22 17:50:04 +01:00 |
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Luke Wren
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e4b0d999cb
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Minor doc updates
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2021-07-18 20:45:08 +01:00 |
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Luke Wren
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46f95f859d
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Some doc updates
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2021-07-17 13:07:09 +01:00 |
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Luke Wren
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93c7039ea1
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Sync doc updates
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2021-07-12 22:13:31 +01:00 |
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Luke Wren
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47fa7f4d10
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Associated doc updates
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2021-07-10 18:53:59 +01:00 |
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Luke Wren
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83244c6651
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Add Read ID command to UART DTM
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2021-07-10 16:14:35 +01:00 |
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Luke Wren
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3312ea7022
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Add draft UART DTM
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2021-07-08 17:57:46 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |