Luke Wren
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be80bd4c18
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Radical opinion, we should have good performance by default, not bad
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2022-04-02 17:53:22 +01:00 |
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Luke Wren
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7dc5046505
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Perf option for dedicated branch comparator
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2022-04-02 11:40:47 +01:00 |
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Luke Wren
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b0b8703ea4
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Support up to 128 IRQs
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2022-03-13 09:27:43 +00:00 |
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Luke Wren
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bf15b6c49f
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Fix forward reference to net
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2022-01-18 23:02:39 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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c5e85dea4c
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Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
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Luke Wren
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c8afb4ac33
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Add option for fast high-half multiplies
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2021-11-29 18:48:02 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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3312ea7022
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Add draft UART DTM
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2021-07-08 17:57:46 +01:00 |
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Luke Wren
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6a38fc33a6
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Allow MHARTID to be configured at instantiation
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2021-07-07 16:08:08 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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12851d3742
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Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
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2021-05-30 19:52:46 +01:00 |
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Luke Wren
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565b76672a
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Make MVENDORID/MARCHID/MIMPID configurable
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2021-05-30 18:42:43 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |