Luke Wren
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c41fe0609b
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Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
Fix a couple of minor test script issues.
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2023-03-26 23:00:18 +01:00 |
Scott Shawcroft
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7fbdb69328
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Allow reconnecting to the testbench JTAG socket
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2022-12-17 11:58:14 +00:00 |
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Luke Wren
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9e2f5df00a
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Add testbench flag to propagate CPU return code to testbench return
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2022-05-28 15:00:28 +01:00 |
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Luke Wren
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cfed35b3da
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Fix the stupid printf warning on x86-64 as well as arm64
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2022-05-24 18:22:25 +01:00 |
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Luke Wren
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4ba3f7ceb9
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Fix format warning in tb.cpp on arm64
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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a81d129961
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Add exclusives monitor to testbench
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2021-12-17 17:03:35 +00:00 |
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Luke Wren
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5ab60422ad
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Add minimal multicore launch code
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2021-12-17 01:24:11 +00:00 |
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Luke Wren
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207566660d
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tb: handle both ports identically. Preparing for dual core
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2021-12-17 00:04:00 +00:00 |
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Luke Wren
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9fb2af800f
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Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
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2021-12-12 14:58:50 +00:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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c1f17b0b23
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Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
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2021-11-06 09:59:27 +00:00 |
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Luke Wren
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2618ae0c07
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Double-step() after clock posedge to workaround CXXRTL port propagation issue
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2021-07-18 16:03:53 +01:00 |
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Luke Wren
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ce5cc1f150
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oops, bounds checking on free-running tb_cxxrtl
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2021-07-18 15:20:25 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |