449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
cd1b391714
More docs cleanup
2021-12-02 02:29:34 +00:00
ebe87dce46
Reorganise CSR section of docs
2021-12-02 01:35:18 +00:00
c5e85dea4c
Add mconfigptr CSR
2021-12-01 03:25:56 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
9bf4d5105f
Describe possible debug topologies. Update pdf.
2021-11-28 09:01:23 +00:00
4e2686d4ab
Finish documenting CSRs. Draw a debug topology diagram.
2021-11-28 08:17:23 +00:00
76172cdade
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
2021-11-28 06:33:35 +00:00
79c29354d2
Update docs with bitmanip instructions
2021-11-28 03:16:45 +00:00
5f8d217395
Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
2021-05-31 17:54:12 +01:00
4053458485
Document some IRQ CSRs, and instruction timings
2021-05-31 15:57:05 +01:00
Luke Wren