Luke Wren
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d9389fb23e
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Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
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2022-06-16 01:42:28 +01:00 |
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Luke Wren
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f8aad6d2f3
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Fix some bugs, too tired to list them, look at the diff
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2022-06-15 04:05:31 +01:00 |
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Luke Wren
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0766ec6f8a
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First pass at adding branch prediction
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2022-06-15 02:05:46 +01:00 |
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Luke Wren
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e68d8a6cd6
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Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
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2022-06-13 01:23:32 +01:00 |
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Luke Wren
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26d54d0023
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Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
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2022-06-12 21:01:39 +01:00 |
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Luke Wren
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ea2b8888a4
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Update copyright years
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2022-06-09 00:12:01 +01:00 |
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Luke Wren
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81aec325bb
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ecall from U-mode has a different mcause value than ecall from M-mode
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2022-05-28 12:07:29 +01:00 |
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Luke Wren
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51750eb81d
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Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
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2022-05-24 21:12:44 +01:00 |
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Luke Wren
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210dbeae64
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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Luke Wren
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43e0b1d16a
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Implement Zbkb (untested)
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2022-05-06 17:36:25 +01:00 |
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Luke Wren
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2c8f3974d0
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Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
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2022-04-09 13:49:16 +01:00 |
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Luke Wren
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887c93dbf0
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Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
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2022-03-02 18:35:16 +00:00 |
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Luke Wren
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28b53ef7b5
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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Luke Wren
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7485269ddf
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Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
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2021-12-17 22:36:40 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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7d2fa6a049
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Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
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2021-12-09 06:26:31 +00:00 |
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Luke Wren
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260491405a
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Fix atomic instructions not asserting decode error when A extension is disabled
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2021-12-06 07:28:50 +00:00 |
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Luke Wren
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12c79c0b41
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Fix feature-flag for Zbs instructions in decoder
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2021-12-05 02:05:35 +00:00 |
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Luke Wren
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5c098866f2
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Sketch in AMO support
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2021-12-04 20:46:39 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
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Luke Wren
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cc6a6c09ba
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Vaguely implement wfi
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2021-11-05 18:48:42 +00:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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4b9a3c2c78
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Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
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2021-05-29 19:32:12 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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5e61c9f9ac
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Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
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2021-05-23 09:12:50 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |
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Luke Wren
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7a3ce494e4
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Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
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2021-05-23 06:40:44 +01:00 |
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Luke Wren
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dec78a728d
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Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
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2021-05-22 15:35:52 +01:00 |
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Luke Wren
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692abbad8b
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Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
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2021-05-22 07:55:13 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |