Luke Wren
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e68d8a6cd6
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Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
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2022-06-13 01:23:32 +01:00 |
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Luke Wren
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26d54d0023
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Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
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2022-06-12 21:01:39 +01:00 |
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Luke Wren
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e3da922f8b
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Revert previous frontend changes. Seemed promising but is a dead end for area.
The original frontend design can probably be tweaked to support predictions.
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2022-06-12 16:25:42 +01:00 |
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Luke Wren
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940b7e4009
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Actually still need 7 halfwords for full throughput in the case of sequential word-sized halfword-aligned instructions
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2022-06-12 16:21:56 +01:00 |
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Luke Wren
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8458dff083
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Fix bus errors not being applied in frontend
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2022-06-12 05:28:21 +01:00 |
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Luke Wren
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23b4dbe7f3
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Redesign fetch queue: 2x32 + 3x16 -> 6x16.
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
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2022-06-12 02:44:08 +01:00 |
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Luke Wren
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d5a202e4a5
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Add standalone frontend formal tb
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2022-06-11 20:14:24 +01:00 |
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Luke Wren
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3b5879da66
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Small code cleanup in frontend. The address phase alignment state no longer needs to be tracked, since we just generate word accesses always, for simplicity.
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2022-06-11 14:27:59 +01:00 |
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Luke Wren
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de9b51b787
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Remove default zeroing of fetch address when no fetch is asserted -- this puts LUTs on a critical path and arguably causes more toggling than asserting the sequentially next address by default.
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2022-06-11 14:26:40 +01:00 |
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Luke Wren
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ea2b8888a4
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Update copyright years
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2022-06-09 00:12:01 +01:00 |
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Luke Wren
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c93228d13e
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Integrate PMP, and fix a couple of PMP bugs
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2022-05-24 19:57:45 +01:00 |
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Luke Wren
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4878a752d6
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Plumb privilege state through to the bus ports
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2022-05-24 18:24:34 +01:00 |
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Luke Wren
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35651f52a7
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Stronger property for correct predecode
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2022-04-05 08:18:00 +01:00 |
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Luke Wren
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20cf408632
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Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing.
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2022-04-04 20:16:19 +01:00 |
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Luke Wren
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357efac66e
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Don't decode unnecessary bits in register predecode logic
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2022-04-04 18:22:09 +01:00 |
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Luke Wren
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3c61fae9ef
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Remove the halfword fetch thing, was only really useful on RISCBoy
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2022-04-02 10:54:16 +01:00 |
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Luke Wren
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887c93dbf0
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Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
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2022-03-02 18:35:16 +00:00 |
Luke Wren
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8fbffbe133
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Assign full width of fifo_valid in non-reset clause (cosmetic fix)
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2022-02-24 12:00:27 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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116e34df49
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Fix commented out frontend properties which relied on non-constant past reset values
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2021-12-07 20:24:29 +00:00 |
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Luke Wren
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ed6b6a3660
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Cleanup order of declaration/use of a couple of wires
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2021-11-25 15:16:59 +00:00 |
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Luke Wren
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e05e9a4109
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Add default_nettype none at top of every file, and default_nettype wire at bottom
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2021-11-23 22:10:39 +00:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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5cc483898d
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Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
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2021-07-10 21:02:18 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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cc6f590f2e
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Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
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2021-05-22 10:16:02 +01:00 |
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Luke Wren
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692abbad8b
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Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
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2021-05-22 07:55:13 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |