e89ab0d095
tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ
...
(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.
2023-03-31 02:11:52 +01:00
97121afa91
Extend testbench to allow dumping/replaying JTAG to text file.
...
This allows debugging of tests that behave differently when VCD dumping
is enabled, due to the difference in execution speed.
(A couple of the SMP debug tests fail intermittently.)
2023-03-27 00:17:11 +01:00
c41fe0609b
Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
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Fix a couple of minor test script issues.
2023-03-26 23:00:18 +01:00
7fbdb69328
Allow reconnecting to the testbench JTAG socket
2022-12-17 11:58:14 +00:00
9e2f5df00a
Add testbench flag to propagate CPU return code to testbench return
2022-05-28 15:00:28 +01:00
cfed35b3da
Fix the stupid printf warning on x86-64 as well as arm64
2022-05-24 18:22:25 +01:00
4ba3f7ceb9
Fix format warning in tb.cpp on arm64
2022-05-24 16:17:54 +01:00
a81d129961
Add exclusives monitor to testbench
2021-12-17 17:03:35 +00:00
5ab60422ad
Add minimal multicore launch code
2021-12-17 01:24:11 +00:00
207566660d
tb: handle both ports identically. Preparing for dual core
2021-12-17 00:04:00 +00:00
9fb2af800f
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
2021-12-12 14:58:50 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
c1f17b0b23
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
2021-11-06 09:59:27 +00:00
2618ae0c07
Double-step() after clock posedge to workaround CXXRTL port propagation issue
2021-07-18 16:03:53 +01:00
ce5cc1f150
oops, bounds checking on free-running tb_cxxrtl
2021-07-18 15:20:25 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
Luke Wren
Scott Shawcroft