Luke Wren a8933c332d Fix illegal issue of pipelined exclusives on the bus, and document correct timings		2021-12-04 18:23:01 +00:00
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arith	Add option for fast high-half multiplies	2021-11-29 18:48:02 +00:00
debug	Remove UART DTM	2021-12-02 02:08:16 +00:00
peri	Add default_nettype none at top of every file, and default_nettype wire at bottom	2021-11-23 22:10:39 +00:00
hazard3.f	More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus	2021-05-29 18:00:43 +01:00
hazard3_config.vh	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_config_inst.vh	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_core.v	Fix illegal issue of pipelined exclusives on the bus, and document correct timings	2021-12-04 18:23:01 +00:00
hazard3_cpu_1port.v	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_cpu_2port.v	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_csr.v	Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.	2021-12-04 01:17:57 +00:00
hazard3_decode.v	Add basic support for lr/sc instructions from the A extension	2021-12-04 15:02:31 +00:00
hazard3_frontend.v	Cleanup order of declaration/use of a couple of wires	2021-11-25 15:16:59 +00:00
hazard3_instr_decompress.v	Add default_nettype none at top of every file, and default_nettype wire at bottom	2021-11-23 22:10:39 +00:00
hazard3_ops.vh	Add RISC-V opcodes and memory operation codes for atomics	2021-12-04 11:16:24 +00:00
hazard3_regfile_1w2r.v	Add default_nettype none at top of every file, and default_nettype wire at bottom	2021-11-23 22:10:39 +00:00
hazard3_width_const.vh	Add RISC-V opcodes and memory operation codes for atomics	2021-12-04 11:16:24 +00:00
rv_opcodes.vh	Add RISC-V opcodes and memory operation codes for atomics	2021-12-04 11:16:24 +00:00