* Fixed typing error in gather test
Deleted the external output tensor creation in scalar_1d test
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
* Added ifdef marco for some later added ops
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
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Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Change type of shape from int to uint & add ut for broadcast
From github issue https://github.com/VeriSilicon/TIM-VX/issues/376
Define opversion to avoid incompatibility with upper level software
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added Tan Cos operaion
Added reduction param in scatternd_onnx_v16
Added R2X bias in bidirectional_lstm
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Resolve the issue of underlying hardware not supporting float16 bias in fc
by converting bias type to float32
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Correct erros of deconv1d unittest
Added hint in the header indicating that padtype is not supported yet
Added 2 cases for deconv1d
Type: Code Improvement
Issue: github issue #585
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added Float16 type definition from third-party
Refine float16 bias handlling in conv2d
Refine float16 case in conv2d
Caution: Headers of float16 only be included when build unit_test
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Remove wrong layout comment for depthwise conv unit test
Add comment of layout condition in basic class for depthwise conv
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Convert float16 bias tensor to float32 to meet condition of NN
convolution in driver
Caution: Clang version requires minimum 15.0
Type: Code Improvement
Issue: bugzilla id:32785 | jira id VIVD-744
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Add another constructor for stridedslice when new_axis_mask is set
The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Layernormolization can handle non zero axis now
Added case to verify layernorm with axis 2
Modify layernorm opjson
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Record constructor form of each operation as a json file to support acuity to call
timvx op
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Refine unidirectional_gru and gru_cell code to avoid including ovxlib files
in header of some op
Introduce TranslateToVsibool function to support above code refinement
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
Chen Feiyue
Antkillerfarm
xie-oritek
chxin66
shijie001
Tang
meseraph
Chen Xin
Feiyue Chen
Qin.Chen
xiang.zhang
MESeraph