Add VexRiscv fpga generation to ecp5.

VexRiscv/Murax.v

@@ -11,13 +11,14 @@ module Murax (
   input               io_jtag_tdi,
   output              io_jtag_tdo,
   input               io_jtag_tck,
-  input      [31:0]   io_gpioA_read,
-  output     [31:0]   io_gpioA_write,
-  output     [31:0]   io_gpioA_writeEnable,
   output              io_uart_txd,
   input               io_uart_rxd
 );
 
+  reg      [31:0]   io_gpioA_read;
+  wire     [31:0]   io_gpioA_write;
+  wire     [31:0]   io_gpioA_writeEnable;
+
   wire       [7:0]    system_cpu_debug_bus_cmd_payload_address;
   wire                system_cpu_dBus_cmd_ready;
   reg                 system_ram_io_bus_cmd_valid;

VexRiscv/fpga/gen/synth.ys

@@ -0,0 +1,5 @@
+read_verilog ../Murax.v
+hierarchy -check -top Murax
+synth -run coarse; opt -fine
+write_verilog -noexpr -noattr gen/synth.v
+synth_ecp5 -top Murax -json gen/soc.json

VexRiscv/fpga/soc.lpf

@@ -0,0 +1,38 @@
+
+LOCATE COMP "io_mainClk" SITE "P3";
+IOBUF PORT "io_mainClk" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_mainClk" 25 MHZ;
+
+LOCATE COMP "io_asyncReset" SITE "N2";
+IOBUF PORT "io_asyncReset" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_asyncReset" 25 MHZ;
+
+LOCATE COMP "rst" SITE "N3";
+IOBUF PORT "rst" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "rst" 25 MHZ;
+
+LOCATE COMP "io_jtag_tck" SITE "T2";
+IOBUF PORT "io_jtag_tck" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_jtag_tck" 25 MHZ;
+
+LOCATE COMP "io_jtag_tms" SITE "T3";
+IOBUF PORT "io_jtag_tms" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_jtag_tms" 25 MHZ;
+
+LOCATE COMP "io_jtag_tdi" SITE "N4";
+IOBUF PORT "io_jtag_tdi" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_jtag_tdi" 25 MHZ;
+
+LOCATE COMP "jtag_trst_n" SITE "M3";
+IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "jtag_trst_n" 25 MHZ;
+
+LOCATE COMP "io_jtag_tdo" SITE "M4";
+IOBUF PORT "io_jtag_tdo" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "io_uart_rxd" SITE "P4";
+IOBUF PORT "io_uart_rxd" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "io_uart_rxd" 25 MHZ;
+
+LOCATE COMP "io_uart_txd" SITE "N3";
+IOBUF PORT "io_uart_txd" IO_TYPE=LVCMOS33;

VexRiscv/fpga/synth.sh

@@ -0,0 +1,49 @@
+#!/bin/bash
+set -ex
+
+SOC=../Murax.v
+
+YOSYS_COARSE=true
+YOSYS_GLOBRST=false
+YOSYS_SPLITNETS=false
+TOP="Murax"
+
+mkdir -p gen
+rm -rf gen/*
+
+{
+	echo "read_verilog ${SOC}"
+
+	if test -n "$TOP"; then
+		echo "hierarchy -check -top $TOP"
+	else
+		echo "hierarchy -check"
+	fi
+	if $YOSYS_GLOBRST; then
+		# insertation of global reset (e.g. for FPGA cores)
+		echo "add -global_input globrst 1"
+		echo "proc -global_arst globrst"
+	fi
+	echo "synth -run coarse; opt -fine"
+	# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
+	if ! $YOSYS_COARSE; then
+		echo "memory_map; techmap; opt; abc -dff; clean"
+	fi
+	if $YOSYS_SPLITNETS; then
+		# icarus verilog has a performance problems when there are
+		# dependencies between the bits of a long vector
+		echo "splitnets; clean"
+	fi
+	if $YOSYS_COARSE; then
+		echo "write_verilog -noexpr -noattr gen/synth.v"
+	else
+		echo "select -assert-none t:\$[!_]"
+		echo "write_verilog -noattr gen/synth.v"
+	fi
+	echo "synth_ecp5 -top $TOP -json gen/soc.json"
+	# echo "synth_xilinx -top $TOP"
+} > gen/synth.ys
+
+yosys -v2 -l gen/synth.log gen/synth.ys
+
+nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 100  --json gen/soc.json