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189 Commits

Author SHA1 Message Date
aprnath 761e69df4e
Update release-notes.md 2019-09-04 17:44:15 -04:00
Joseph Rahmeh 811e9c3d24 Change clock header instance name in beh_lib.sv 2019-09-04 14:39:10 -07:00
Joseph Rahmeh 35bc589b09 Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV 2019-09-04 13:32:48 -07:00
Joseph Rahmeh b35d7e9e1b Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module. 2019-09-04 13:29:39 -07:00
Ajay Nath fc331027c2 Conditioned declaration of finished per issue #13 2019-09-03 21:35:43 -04:00
tmw-wdc 2108e722c8 Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV 2019-08-13 15:48:48 -07:00
tmw-wdc 68f4383d96 Update RISC-V SweRV EH1 PRM.pdf 
Rev. 1.2
 2019-08-13 15:48:28 -07:00
Joseph Rahmeh 4e161e6c3b Minor cleanup in config script. 2019-08-13 15:47:53 -07:00
jrahmeh 189ce25027
Updated release notes 2019-08-13 16:42:26 -05:00
jrahmeh 8242950a58
Fixed branch numbers 2019-08-13 15:30:00 -05:00
jrahmeh c5a699aa40
Fixed release notes 2019-08-13 15:08:45 -05:00
Joseph Rahmeh d9bb036633 Updated hello world message. Updated last compilation time. 2019-08-13 12:57:04 -07:00
Joseph Rahmeh 7ff8d7fb5a Untabified files. 2019-08-13 12:48:48 -07:00
Joseph Rahmeh 85a510db19 Updated release notes. 2019-08-13 12:43:09 -07:00
Joseph Rahmeh ac92841999 Adjust CSR MFDC reset value for the AXI bus. 2019-08-13 12:38:50 -07:00
Joseph Rahmeh e20f012de7 Removed refernce to version 1.1. 2019-08-10 13:42:48 -07:00
Joseph Rahmeh 40db638de6 Mention 1.1.1 release. 2019-08-10 13:23:53 -07:00
Joseph Rahmeh e7f57a0d5d Added 1.1.1 release notes. 2019-08-10 13:23:08 -07:00
Joseph Rahmeh 6a528a9a8b Ignore ebreak/ecall w.r.t MINSTRET 2019-08-09 19:18:41 -07:00
Joseph Rahmeh 1cf98e765d fix synthesis syntax in rvdffe in beh_lib.sv 2019-08-08 07:51:56 -07:00
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does 
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
 2019-08-07 17:04:48 -07:00
jrahmeh bc367eaf3a
Update README.md 
Added description of "espresso".
 2019-07-20 08:28:44 -05:00
Joseph Rahmeh 8c413fd1e2 Removed invalid include statement. 2019-07-12 11:26:03 -07:00
Joseph Rahmeh e40f01e15d Moved flist.questa to testbench directory. 2019-07-12 11:25:07 -07:00
Joseph Rahmeh 0f3f246df5 Remove spurious carriage return characters. 2019-07-12 06:22:01 -07:00
Joseph Rahmeh 5990932214 Removed apostrophe from comment. 2019-07-12 06:04:31 -07:00
Joseph Rahmeh 412c128fb0 Removed duplicate declaration of finished for Verilator. 2019-06-20 09:50:50 -07:00
Joseph Rahmeh 8f92cd5033 Added .gitignore file. 2019-06-20 08:48:50 -07:00
jrahmeh 48dc8668cb
Update README.md 2019-06-09 19:50:35 -05:00
jrahmeh 166274de5e
Update README.md 
Added reference to version 1.0.
 2019-06-06 11:32:35 -05:00
jrahmeh 56db557851
Update release-notes.md 2019-06-04 11:31:56 -05:00
Joseph Rahmeh d33df11a5b Added release notes. 2019-06-04 09:29:22 -07:00
joseph rahmeh 9c6d925379 Create RISC-V SweRV EH1 PRM.pdf 2019-06-04 10:54:09 -05:00
Joseph Rahmeh de6978de5d SweRV 1.1 2019-06-04 07:58:40 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00
Zvonimir Bandic 6ccfce0957
Update README.md 2019-06-01 23:45:59 -07:00
Zvonimir Bandic 1abeb9a380
Update README.md 2019-06-01 23:44:30 -07:00
Zvonimir Bandic 763cd3d38a
Create README.md 2019-06-01 23:43:28 -07:00
Zvonimir Bandic 8f1c48c0ab
Initial commit 2019-06-01 23:32:39 -07:00