colin.liang
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c2e4068c8a
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Add uriscv/tb.
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2023-01-07 16:14:56 +08:00 |
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colin.liang
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5fb3787307
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reset from top.v.
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2023-01-06 21:19:54 +08:00 |
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colin.liang
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31c90f22f6
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Refine top.v.
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2023-01-06 16:15:04 +08:00 |
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colin.liang
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c57450fa1c
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Add ivlpp to gen single file of RTL.
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2023-01-05 21:28:53 +08:00 |
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colin.liang
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44161e293f
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Reset Readme.
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2023-01-04 22:40:08 +08:00 |
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colin.liang
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270f695fbf
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Update Readme
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2022-11-03 17:00:26 +08:00 |
colin
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32fff97ff5
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Update gnu build.
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2022-07-07 12:06:04 +00:00 |
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colin
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e23aca0cfc
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Delete rvdff by fpga.
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2022-05-23 15:37:09 +00:00 |
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colin
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a8c8d46382
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Remove ahb connect axi4.
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2022-05-23 14:51:42 +00:00 |
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colin
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902f44a21c
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Default use axi4 without ahb_lite.
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2022-05-23 14:45:23 +00:00 |
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colin
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6bf845bb46
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Format sv and v code.
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2022-05-23 14:16:04 +00:00 |
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colin
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2f8715aeb6
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Delete unuse file and configs.
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2022-05-23 13:53:58 +00:00 |
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colin
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a9bfa80cc1
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Test jtag demo will incorrect when add instruction in loop3.
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2022-05-11 03:31:51 +00:00 |
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colin
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29696841ff
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Refine flow asm code.
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2022-05-10 13:44:14 +00:00 |
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colin
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fd64d8618a
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Copy Cores-SweRV-EL2 to flow.
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2022-05-10 13:07:33 +00:00 |
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colin
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11312aee91
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Refine uriscv to verilator.
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2022-05-10 12:50:30 +00:00 |
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colin
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ded2df85f8
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Refine Readme of uriscv.
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2022-05-10 04:20:23 +00:00 |
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colin
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1dfaaa39ef
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Add uriscv, a smallest riscv implementation.
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2022-05-10 04:19:18 +00:00 |
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colin
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15467611cf
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Update Readme.
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2022-03-27 09:56:02 +00:00 |
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colin
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937a29de67
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Update Cores-EL2 and Quasar.
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2022-03-27 09:55:41 +00:00 |
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colin
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bd392cfb7c
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Refine reset vector in Cores-SweRV.
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2022-03-22 23:25:11 +00:00 |
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colin
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5b6bdcc8b0
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Update .gitignore.
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2022-03-22 23:24:30 +00:00 |
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colin
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388db4a82e
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Delete quasar in Cores-SweRV.
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2022-03-22 23:24:01 +00:00 |
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colin
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386e1f1a54
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Add Miner420T submodule
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2022-03-22 23:14:02 +00:00 |
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colin
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be80eb1063
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Update Quasar.
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2022-03-20 09:06:23 +00:00 |
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colin
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49c8aab2fd
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Update Readme.
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2022-03-20 09:06:02 +00:00 |
|
colin
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03549f1f93
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Update Quasar
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2022-03-18 10:06:26 +00:00 |
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colin
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b2c15ca508
|
Update xilinx Readme.
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2022-03-11 05:08:19 +00:00 |
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colin
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b9d70b7a1c
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Update Quasar
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2022-03-10 13:15:49 +00:00 |
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colin
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d806515276
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Add submodule of quasar.
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2022-03-10 08:58:15 +00:00 |
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colin
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2be1901f7b
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update EL2
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2022-03-09 14:46:24 +00:00 |
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colin
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e513374a7e
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Add submodule of sweRV EL2.
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2022-03-09 11:17:07 +00:00 |
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colin
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beab126fc5
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add quasar fpga.
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2022-03-09 11:16:13 +00:00 |
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colin
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33885bbccb
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Add Bit-Vector install in readme
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2022-03-07 04:08:12 +00:00 |
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colin
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27fade0b6d
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Add EL2 cores implement by Chisel in quaser.
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2022-03-06 04:22:17 +00:00 |
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colin
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0a00e20cfe
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Update riscv gcc version and usage.
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2022-03-06 04:21:41 +00:00 |
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colin
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3da81c5916
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Add install commond in riscv gnu tools.
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2022-03-01 13:22:23 +00:00 |
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colin
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e26d5260de
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start to add ecp5 support,current donet support jlink
Use FT2232H base jtag,and VexRiscv's openocd to support dbg.
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2022-02-28 03:34:59 +00:00 |
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colin
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2c4658ddb9
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Refine murax sim config file
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2022-02-28 03:33:41 +00:00 |
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colin
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28d08fc3ad
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Refine Readme of install openocd.
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2022-02-28 03:33:08 +00:00 |
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colin
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e0f77ceead
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Add configuration to flash by ecpdap.
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2022-02-27 15:39:45 +00:00 |
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colin
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94c99367ba
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remove gen file in fpga
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2022-02-27 04:49:27 +00:00 |
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colin
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1d1237c223
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Add VexRiscv fpga generation to ecp5.
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2022-02-26 15:14:43 +00:00 |
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colin
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25a557365b
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Enable VexRiscv murax jtag simulator by verilator.
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2022-02-26 14:34:25 +00:00 |
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colin
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e3968e6fa7
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Refine opene906 gdb sample.
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2022-02-25 12:24:03 +00:00 |
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colin
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65545d5e03
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Add VexRiscv.
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2022-02-25 11:56:36 +00:00 |
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colin
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ccc993e003
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Refine gdb sample code
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2022-02-24 06:04:58 +00:00 |
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colin
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3258c057e3
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Enable demo openocd and gdb.
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2022-02-24 03:18:07 +00:00 |
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colin
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1d7ba86749
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Add dome on opene906
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2022-02-22 06:44:45 +00:00 |
|
colin
|
0d940ba004
|
Add opene906
|
2022-02-21 10:41:54 +00:00 |