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202 Commits

Author SHA1 Message Date
colin 0d940ba004 Add opene906 2022-02-21 10:41:54 +00:00
colin 51730ed20d Add xilinx readme. 2022-02-21 07:53:02 +00:00
colin 3972a891ca Add fpga demo in Cores. 2022-02-21 07:52:52 +00:00
colin 3edc87e0ea Switch mem bus from ahb to axi. 2022-02-17 11:35:01 +00:00
colin cffec82632 Add clean before fpga ram make all 2022-02-17 06:21:42 +00:00
colin 8e190efed0 Split from soc.mk to soc_sim.mk and soc_top.mk 2022-02-15 08:31:00 +00:00
colin 1f222dd1e3 Split soc and verilator to two part system verilog. 2022-02-14 12:32:21 +00:00
colin a6038fde4a Set DCCM and ICCM size to 32KB 2022-02-11 12:17:21 +00:00
colin 547f0dbdc3 remove axi4 in demo soc use ahb as default 2022-02-10 12:17:10 +00:00
colin 18c8352c09 Add ram test and verilator in fpga DEMO. 2022-02-09 12:47:35 +00:00
colin 3c3cfccfd5 add ram test. 2022-02-08 03:00:40 +00:00
colin a7ef641f0d Refine io level 2022-02-07 13:34:50 +00:00
colin 3405c88c9e Correct blink and use sample blink code 2022-02-07 13:23:34 +00:00
colin 3370d01917 Add verilator install method in readme. 2022-02-07 08:13:16 +00:00
colin 3ba8533996 Add fpga 2022-02-02 03:43:53 +00:00
colin a15c797e93 add jtag to ESP32 2022-02-02 03:40:41 +00:00
colin 853d12f17c Init to abstract accelerator project 2022-02-02 03:34:37 +00:00
colin f299211d91 Refine readme for rocket tool build 2022-02-01 15:50:30 +00:00
Colin d8c2a6861b refine Readme for demo 2022-01-27 16:42:31 +08:00
Colin 3ed8011eaa add jtag demo for GDB which openocd 2022-01-22 08:08:47 +00:00
Colin 5f80832b1a add jtag demo and refine Makefile 2022-01-20 03:44:59 +00:00
Colin a8fc3642ad Add dpi of jtag 2022-01-19 12:45:38 +00:00
Colin 65f5085afa refine makefile 2022-01-19 09:57:37 +00:00
Colin 9174bfe249 mv flist to soc folder 2022-01-17 12:18:33 +00:00
Colin 1437f0fcf3 move swerv config and json to soc 2022-01-17 12:14:05 +00:00
Colin 7aff1ae5f1 add soc for common test with soc. 2022-01-17 11:53:50 +00:00
Colin 3be1146718 refine define file build 2022-01-17 11:40:11 +00:00
Colin 1d8069026b remove no use file in demo 2022-01-17 11:10:22 +00:00
Colin 2b298f0fff rename test to demo 2022-01-17 06:43:14 +00:00
Colin 0eb74fdc10 refine test use function 2022-01-05 03:47:27 +00:00
Colin 6567357739 add llvm build flow from .c file 2022-01-04 12:39:14 +00:00
Colin be63e84a1d Add build from llvm 2021-12-17 13:29:59 +00:00
Colin 911f65874f add test of verilator in one folder 2021-12-16 12:08:59 +00:00
Ajay Nath 87c23b9952
Merge pull request #101 from antmicro/fix-vivado-tcl 
Remove not existing file from vivado.tcl
 2021-10-08 17:45:03 -04:00
Kamil Rakoczy f57cce19ff Remove not existing file from vivado.tcl 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-08-27 15:27:02 +02:00
Ajay Nath 81bff1c0d7 reverting to 0242c9e for swerv_config_gen.py 2021-03-12 08:02:57 -05:00
Ajay Nath d4e7b25f71
Merge pull request #93 from antmicro/variable-order-fix 
Declare variables before using them
Thank you for this update.
 2021-02-19 15:03:43 -05:00
Tomasz Gorochowik 74a6bdb50d Do not use variables before declaration 2021-02-17 17:09:35 +01:00
Ajay Nath f3da044f15
Delete testbench/tests/cmark_dccm directory 
This directory is redundant due to the reworking of test flow in release 1.9
 2021-02-16 08:56:23 -05:00
Thomas Wicki 5e23462bd0
Update README.md 2021-02-03 13:26:41 -08:00
Joseph Rahmeh 695883a674 Removed dead code. 2021-02-03 11:08:48 -08:00
Joseph Rahmeh 0c92ea167b Version 1.9 2021-02-03 07:07:10 -08:00
Joseph Rahmeh ec254f5491 Version 1.9. 2021-01-27 09:36:43 -08:00
Ajay Nath bcb5b33726
Merge pull request #82 from chipsalliance/quartus_core_fix 
Only load Vivado TCL files when using Vivado
 2021-01-21 17:59:41 -05:00
Ajay Nath bb9f9ef37b
Merge pull request #89 from olofk/scan_mode 
Remove unused scan_mode input from dmi_wrapper.
We will be releasing some fixes shortly which will have this change too. Accepting your PR so as not hold up any progress.
 2021-01-21 17:58:36 -05:00
Olof Kindgren bcf505751e Remove unused scan_mode input from dmi_wrapper 
This causes the dmi wrapper from SweRV EH1 and SweRV EL2 to have
the same interface which makes it easier to use the two CPU cores
interchangeably in a design.
 2021-01-18 10:15:08 +01:00
Olof Kindgren 3918a8d345
Only load Vivado TCL files when using Vivado 
This prevents the vivado-specific TCL file to be loaded when using the synth target with other synthesis tools than vivado
 2020-11-24 09:31:52 +01:00
Ajay Nath 7332edc0ad
Merge pull request #76 from olofk/snapshot_dir2 
Set snapshot dir to a known location in FuseSoC SweRV config generator
 2020-09-24 10:26:32 -04:00
Olof Kindgren 0242c9e6d2 Explicitly use python3 2020-09-24 15:24:30 +02:00
Olof Kindgren 801d0f66f6 Set snapshot dir to a known location in FuseSoC SweRV config generator 
The previous fix for the FuseSoC SweRV config generator was not complete
 2020-09-24 14:32:08 +02:00