e3b3893cdf
Fix partial case overlap lint for shared A/Zbb ALU ops
2024-06-06 06:58:59 +01:00
d1f1421728
Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl. All cosmetic.
2024-05-29 15:52:53 +01:00
360b034f76
Fix a few width issues identified by verilator lint. All of them gave
...
well-defined correct results already (i.e. correctly zero-extended per
spec) but best to avoid the noise.
2024-05-26 17:32:24 +01:00
aa438fc37c
Remove op_b (rs2) register from muldiv_seq for modest LUT/FF savings
2022-10-08 18:22:16 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
5d6b5a80b0
Standardise on ifndef YOSYS around default_nettype wire
2022-08-21 13:22:55 +01:00
3b7cd9bc96
Cleanup some unused signals
2022-08-20 16:44:39 +01:00
ef927d0d23
Dumb typo
2022-08-08 10:26:36 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
b7d9defcf2
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
2022-07-05 03:37:19 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
...
and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
210dbeae64
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
43e0b1d16a
Implement Zbkb (untested)
2022-05-06 17:36:25 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
7485269ddf
Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
2021-12-17 22:36:40 +00:00
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
0b3629564c
Don't apply shifter assertions to rotates
2021-12-06 18:12:23 +00:00
5c098866f2
Sketch in AMO support
2021-12-04 20:46:39 +00:00
34e57f0b14
Sketch in an AMO ALU
2021-12-04 18:52:41 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
800b21d2f5
Remove event feedback path (not logical path) in priority encoder
2021-11-28 02:19:01 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
5d093487b7
Update README
2021-11-26 23:33:46 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
8bcec11c80
Couple more silly mistakes
2021-11-26 01:30:13 +00:00
41eeb90c7d
Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
2021-11-26 01:29:47 +00:00
998f3fdeb7
Clean up silly mistakes
2021-11-26 00:55:57 +00:00
58c20a39d0
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
2021-11-25 23:30:35 +00:00
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
8cdde82248
Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
2021-07-20 00:13:26 +01:00
af684c4e82
Some cleanup; correctly decode 16-bit EBREAK
2021-06-03 20:03:43 +01:00
844fa8f97f
Rename hazard5 -> hazard3
2021-05-21 03:46:29 +01:00
5de4f01aae
Change how constants are plumbed through the hierarchy. Some small cleanups of variable declaration order etc
2021-05-21 03:23:44 +01:00
6dad4e20bb
Import from hazard5 9743a1b
2021-05-21 02:34:16 +01:00
Luke Wren
Luke Wren