054c4a6a9c
Fix reversed pseudocode for ctz/clz
2022-08-02 21:21:44 +01:00
adf81abfdc
Oops, description of shxadd had operands swapped
2022-07-31 17:45:14 +01:00
e76b82e447
More thoughts about interrupts, starting to look plausible
2022-07-31 16:16:16 +01:00
106c4c3d28
Update docs CSR section to reflect addition of U-mode, PMP etc.
2022-07-30 21:19:30 +01:00
c73c09a48a
More thinking about interrupt priorities
2022-07-30 15:42:26 +01:00
7946432d7a
Speculatively update docs with new interrupt array/priority stuff, and sleep register
2022-07-28 01:18:13 +01:00
ae30d7c0d2
Add instruction pseudocode (no A extension)
2022-07-10 19:16:43 +01:00
956b386a20
Update instruction listings in docs
2022-07-10 05:47:19 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
1697192c62
Fix cycle timing docs for sc.w: 2 cycles if next instruction is RAW-dependent.
2021-12-12 20:50:26 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
1b722b5f27
Add mcycle test, fix incorrect description of mcycle in docs
2021-12-11 21:21:31 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
9e7ea4adb6
Fix column width
2021-12-06 17:14:23 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
a8933c332d
Fix illegal issue of pipelined exclusives on the bus, and document correct timings
2021-12-04 18:23:01 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
cd1b391714
More docs cleanup
2021-12-02 02:29:34 +00:00
ebe87dce46
Reorganise CSR section of docs
2021-12-02 01:35:18 +00:00
c5e85dea4c
Add mconfigptr CSR
2021-12-01 03:25:56 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
0fafae1ab1
Regenerate PDF
2021-11-28 16:27:54 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
9bf4d5105f
Describe possible debug topologies. Update pdf.
2021-11-28 09:01:23 +00:00
4e2686d4ab
Finish documenting CSRs. Draw a debug topology diagram.
2021-11-28 08:17:23 +00:00
76172cdade
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
2021-11-28 06:33:35 +00:00
79c29354d2
Update docs with bitmanip instructions
2021-11-28 03:16:45 +00:00
2aac3d4f91
Add attempt at CPU backend diagram
2021-11-23 22:14:55 +00:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
e4b0d999cb
Minor doc updates
2021-07-18 20:45:08 +01:00
46f95f859d
Some doc updates
2021-07-17 13:07:09 +01:00
93c7039ea1
Sync doc updates
2021-07-12 22:13:31 +01:00
47fa7f4d10
Associated doc updates
2021-07-10 18:53:59 +01:00
83244c6651
Add Read ID command to UART DTM
2021-07-10 16:14:35 +01:00
3312ea7022
Add draft UART DTM
2021-07-08 17:57:46 +01:00
5f8d217395
Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
2021-05-31 17:54:12 +01:00
4053458485
Document some IRQ CSRs, and instruction timings
2021-05-31 15:57:05 +01:00
Luke Wren