Luke Wren
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14a4f1a281
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Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
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2021-11-27 17:19:41 +00:00 |
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Luke Wren
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6f1a10724b
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Add bitmanip test vector generation script
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2021-11-26 23:34:06 +00:00 |
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Luke Wren
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5d093487b7
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Update README
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2021-11-26 23:33:46 +00:00 |
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Luke Wren
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1bb7e33b69
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Fix alignment of heap_ptr in init.S. Small ALU cleanup
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2021-11-26 02:59:50 +00:00 |
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Luke Wren
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7410c52aac
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Update readme
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2021-11-26 02:09:39 +00:00 |
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Luke Wren
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8398d7ecb6
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Hook up Zb* extension params on iCEBreaker FPGA
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2021-11-26 01:44:57 +00:00 |
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Luke Wren
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8bcec11c80
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Couple more silly mistakes
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2021-11-26 01:30:13 +00:00 |
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Luke Wren
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41eeb90c7d
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Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
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2021-11-26 01:29:47 +00:00 |
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Luke Wren
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998f3fdeb7
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Clean up silly mistakes
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2021-11-26 00:55:57 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
Luke Wren
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ed6b6a3660
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Cleanup order of declaration/use of a couple of wires
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2021-11-25 15:16:59 +00:00 |
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Luke Wren
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2aac3d4f91
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Add attempt at CPU backend diagram
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2021-11-23 22:14:55 +00:00 |
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Luke Wren
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e352715fdf
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Fix IO decode in openocd/tb.cpp
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2021-11-23 22:12:51 +00:00 |
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Luke Wren
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49462a8642
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Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
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2021-11-23 22:11:50 +00:00 |
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Luke Wren
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e05e9a4109
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Add default_nettype none at top of every file, and default_nettype wire at bottom
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2021-11-23 22:10:39 +00:00 |
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Luke Wren
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0b9b706e81
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Safer logic for load/store blocked by preceding WFI
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2021-11-23 22:01:14 +00:00 |
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Luke Wren
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4d14203586
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Update riscv-tests fork for crash loop debug test
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2021-11-23 21:58:39 +00:00 |
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Luke Wren
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60f364e561
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Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
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2021-11-21 15:55:52 +00:00 |
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Luke Wren
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ba9a7b4a03
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Fix broken link in readme
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2021-11-21 14:58:07 +00:00 |
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Luke Wren
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c1f17b0b23
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Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
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2021-11-06 09:59:27 +00:00 |
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Luke Wren
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cc6a6c09ba
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Vaguely implement wfi
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2021-11-05 18:48:42 +00:00 |
Richard-Gordon
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375a6d60b7
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Correct mnemonic when logging unsigned sltiu instruction
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2021-10-08 12:02:37 +01:00 |
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Luke Wren
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cfe16caf41
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Remove some old todos
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2021-09-05 22:20:40 +01:00 |
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Luke Wren
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e9fccffca0
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Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
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2021-09-05 04:45:38 +01:00 |
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Luke Wren
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65bfca5fdf
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Fix latent bug with asynchronous debug entry during stalled load/store address phase
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2021-09-04 07:49:29 +01:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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9173bcf585
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Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
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2021-08-21 17:04:15 +01:00 |
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Luke Wren
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e16ae06cb5
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Clean up timer
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2021-08-21 17:03:32 +01:00 |
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Luke Wren
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9dd091b7b5
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Doh typo
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2021-08-21 09:06:20 +01:00 |
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Luke Wren
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b99e5b8a67
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Convert timer to serial for smaller area. Rather untested
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2021-08-20 22:27:15 +01:00 |
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Luke Wren
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4aba165166
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First pass at a 64-bit system timer
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2021-08-20 21:49:05 +01:00 |
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Luke Wren
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924967ee72
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Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k
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2021-07-25 13:41:04 +01:00 |
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Luke Wren
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5976a8a9b7
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Add activity LED to iCEBreaker
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2021-07-25 13:13:41 +01:00 |
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Luke Wren
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91edd62ea1
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Bump libfpga for FIFO coding style tweak
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2021-07-24 22:06:57 +01:00 |
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Luke Wren
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8263ee3a5d
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Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
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2021-07-24 15:31:33 +01:00 |
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Luke Wren
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6fcc74a043
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Add some instructions to Readme
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2021-07-24 11:53:08 +01:00 |
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Luke Wren
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70a44d9681
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Small code cleanup
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2021-07-24 10:08:27 +01:00 |
Vadzim Dambrouski
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2b1dee4bcc
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Fix broken submodule path
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2021-07-24 09:55:06 +01:00 |
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Luke Wren
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155d3ba554
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Tie off 1 or 2 LSBs of DPC depending on IALIGN
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2021-07-23 23:09:03 +01:00 |
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Luke Wren
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115cb2c50f
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Tweaks to example soc configuration
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2021-07-23 23:08:23 +01:00 |
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Luke Wren
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279e4b4f29
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Implement mstatush as hardwired-0, as required by priv-1.12
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2021-07-23 21:52:01 +01:00 |
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Luke Wren
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2ae30183aa
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Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
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2021-07-23 18:32:47 +01:00 |
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Luke Wren
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8ceae7e9e6
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Start hacking on ECP5 JTAG DTM
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2021-07-23 00:36:55 +01:00 |
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Luke Wren
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41477ce479
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Extract DTM bus/control logic from the JTAG-related parts
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2021-07-22 19:26:25 +01:00 |
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Luke Wren
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b0d11c0ab7
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Add RISC-V debug tests
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2021-07-22 17:50:04 +01:00 |
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Luke Wren
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c14960ee1b
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Add mtime/mtimecmp to openocd testbench
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2021-07-22 17:31:26 +01:00 |
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Luke Wren
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5d2a562f65
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Just use read_verilog; write_cxxrtl when building tb_cxxrtl
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2021-07-22 17:30:30 +01:00 |
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Luke Wren
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8cdde82248
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Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
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2021-07-20 00:13:26 +01:00 |
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Luke Wren
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7d24f42da9
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Oops, properly fix platform IRQ mcause numbers
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2021-07-19 09:32:59 +01:00 |
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Luke Wren
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65fb62901e
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Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
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2021-07-19 00:19:56 +01:00 |