26d54d0023
Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
2022-06-12 21:01:39 +01:00
e3da922f8b
Revert previous frontend changes. Seemed promising but is a dead end for area.
...
The original frontend design can probably be tweaked to support predictions.
2022-06-12 16:25:42 +01:00
940b7e4009
Actually still need 7 halfwords for full throughput in the case of sequential word-sized halfword-aligned instructions
2022-06-12 16:21:56 +01:00
8458dff083
Fix bus errors not being applied in frontend
2022-06-12 05:28:21 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
...
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
3b5879da66
Small code cleanup in frontend. The address phase alignment state no longer needs to be tracked, since we just generate word accesses always, for simplicity.
2022-06-11 14:27:59 +01:00
de9b51b787
Remove default zeroing of fetch address when no fetch is asserted -- this puts LUTs on a critical path and arguably causes more toggling than asserting the sequentially next address by default.
2022-06-11 14:26:40 +01:00
11596a5bd7
Remove unused/untested RISC-V timer implementation
2022-06-09 00:12:26 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
ae2784d0ea
PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.
2022-06-03 17:09:43 +01:00
e0a9fb7312
Add option to hardwire PMP regions, or reduce their granularity
2022-06-03 01:19:03 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
0e462574b2
Move declaration of x_exec_pmp_fail to before its first use
2022-05-27 15:04:43 +01:00
156fbcd019
Update behaviour of mstatus.mpp and mprv on mret to match priv-1.12 spec
2022-05-26 00:42:50 +01:00
a17b941e38
Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
2022-05-25 23:46:23 +01:00
0efcf53fe5
Fix X PMP fail not suppressing load/store address phase.
...
Fix PMP-failed load/store still passing on a data phase tag to stage 3.
Fix WFI still pausing the core after a PMP X fail.
2022-05-25 16:18:03 +01:00
e2b9a3b2f9
Fix two PMP-related bugs:
...
1. Generating PMP load/store exceptions when the instruction is not a load/store
2. Passing a PMP exec permission exception into M whilst the frontend is still
starved, causing early taking of the exception and a bad mepc value.
2022-05-25 13:23:44 +01:00
51750eb81d
Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
2022-05-24 21:12:44 +01:00
c93228d13e
Integrate PMP, and fix a couple of PMP bugs
2022-05-24 19:57:45 +01:00
4878a752d6
Plumb privilege state through to the bus ports
2022-05-24 18:24:34 +01:00
f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
d62861159f
First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
2022-05-24 16:17:54 +01:00
2df1179994
Wire privilege through from core to bus masters. Tied off inside core.
2022-05-24 14:05:26 +01:00
c0b5d73cbd
Typo in for loop, surprised Yosys accepted this
2022-05-23 18:15:36 +01:00
5466c8131e
Sketch in PMP implementation
2022-05-23 18:06:23 +01:00
06647b78c6
Fix IALIGN fault to trap on the control flow instruction instead of its target
2022-05-23 16:25:43 +01:00
da244f54c3
Remove unused FAKE_DUALPORT option from regfile
2022-05-23 16:22:01 +01:00
f849517202
Split CSR addresses into separate header file
2022-05-23 15:54:37 +01:00
5f4127948d
Add a parameter to control register file reset, instead of the weird ifdef tree
2022-05-23 13:29:44 +01:00
df0fd536eb
Fix IRQ priority to match the priv spec
2022-05-23 12:56:37 +01:00
96a9ee18e1
Add IALIGN exception to non-RVC implementations
2022-05-23 12:47:48 +01:00
c4e81922da
Don't store bit 1 of mepc on non-RVC implementations
2022-05-23 12:27:07 +01:00
210dbeae64
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
a2582976fc
Fix opcodes for zip/unzip, which are wrong in the bitmanip copy of the Zbkb spec, but correct in the crypto copy of that spec
2022-05-20 15:15:37 +01:00
43e0b1d16a
Implement Zbkb (untested)
2022-05-06 17:36:25 +01:00
2c8f3974d0
Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
2022-04-09 13:49:16 +01:00
35651f52a7
Stronger property for correct predecode
2022-04-05 08:18:00 +01:00
20cf408632
Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing.
2022-04-04 20:16:19 +01:00
357efac66e
Don't decode unnecessary bits in register predecode logic
2022-04-04 18:22:09 +01:00
be80bd4c18
Radical opinion, we should have good performance by default, not bad
2022-04-02 17:53:22 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
7b8fe43c1c
Fix bad timing of predecoded regnum register update (thanks BMC)
2022-04-02 10:11:55 +01:00
b80b09afe5
Typo -- fully encode all 128 possible IRQs
2022-03-15 09:01:55 +00:00
b0b8703ea4
Support up to 128 IRQs
2022-03-13 09:27:43 +00:00
887c93dbf0
Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
2022-03-02 18:35:16 +00:00
Luke Wren
Luke Wren