5976a8a9b7
Add activity LED to iCEBreaker
2021-07-25 13:13:41 +01:00
91edd62ea1
Bump libfpga for FIFO coding style tweak
2021-07-24 22:06:57 +01:00
8263ee3a5d
Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
2021-07-24 15:31:33 +01:00
6fcc74a043
Add some instructions to Readme
2021-07-24 11:53:08 +01:00
70a44d9681
Small code cleanup
2021-07-24 10:08:27 +01:00
2b1dee4bcc
Fix broken submodule path
2021-07-24 09:55:06 +01:00
155d3ba554
Tie off 1 or 2 LSBs of DPC depending on IALIGN
2021-07-23 23:09:03 +01:00
115cb2c50f
Tweaks to example soc configuration
2021-07-23 23:08:23 +01:00
279e4b4f29
Implement mstatush as hardwired-0, as required by priv-1.12
2021-07-23 21:52:01 +01:00
2ae30183aa
Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
2021-07-23 18:32:47 +01:00
8ceae7e9e6
Start hacking on ECP5 JTAG DTM
2021-07-23 00:36:55 +01:00
41477ce479
Extract DTM bus/control logic from the JTAG-related parts
2021-07-22 19:26:25 +01:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
c14960ee1b
Add mtime/mtimecmp to openocd testbench
2021-07-22 17:31:26 +01:00
5d2a562f65
Just use read_verilog; write_cxxrtl when building tb_cxxrtl
2021-07-22 17:30:30 +01:00
8cdde82248
Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
2021-07-20 00:13:26 +01:00
7d24f42da9
Oops, properly fix platform IRQ mcause numbers
2021-07-19 09:32:59 +01:00
65fb62901e
Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
2021-07-19 00:19:56 +01:00
70443fa557
Disable shifting of MIE/MPIE stack when in or entering debug mode
2021-07-18 21:14:11 +01:00
e4b0d999cb
Minor doc updates
2021-07-18 20:45:08 +01:00
d30fc46f5b
Fix IRQ mcause not being set correctly when vectoring is disabled
2021-07-18 20:44:39 +01:00
c56c75e14b
More dicking with yosys cmd for tb_cxxrtl;
...
Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
2021-07-18 16:46:00 +01:00
12bf9bb570
Make CXXRTL testbench ~25% faster
2021-07-18 16:04:19 +01:00
2618ae0c07
Double-step() after clock posedge to workaround CXXRTL port propagation issue
2021-07-18 16:03:53 +01:00
ce5cc1f150
oops, bounds checking on free-running tb_cxxrtl
2021-07-18 15:20:25 +01:00
e95b465e26
Typo in address of mcountinhibit!
2021-07-17 19:27:01 +01:00
d9300ee127
Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry
2021-07-17 19:26:45 +01:00
8014239d47
openocd tb: report AHB error response when processor accesses outside of RAM/IO
2021-07-17 19:26:05 +01:00
5deff12f95
DM: don't report as running/halted in dmstatus if unavailable.
2021-07-17 16:46:39 +01:00
ab0b4a04f0
Also support progbuf in abstractauto.
2021-07-17 15:08:00 +01:00
46f95f859d
Some doc updates
2021-07-17 13:07:09 +01:00
14ba030271
Example soc tweaks, add openocd config
2021-07-16 20:44:25 +01:00
8e3dc62b97
Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
2021-07-16 20:43:24 +01:00
5aca6be572
Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
2021-07-16 18:28:30 +01:00
ce5152a4f4
Implement HALTSUM0 and HALTSUM1 registers
2021-07-16 17:58:28 +01:00
62822b2e1d
Couple of usability improvements for openocd testbench
2021-07-15 19:42:49 +01:00
011008efd1
Fix detection of exception-like vs IRQ-like halt/trap entries
2021-07-15 19:41:35 +01:00
71ec9fa283
Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
2021-07-14 20:39:51 +01:00
9643a57ba9
Slightly less braindead TCP interactions for openocd JTAG bitbang testbench, much more interactive now
2021-07-14 19:20:27 +01:00
f4952ab66d
Add simple example SoC, hangs nextpnr for some reason!
2021-07-13 03:40:06 +01:00
307955c810
Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
2021-07-13 01:10:55 +01:00
93c7039ea1
Sync doc updates
2021-07-12 22:13:31 +01:00
4b650ac437
DM: add missing w1c to abstract cmderr, add capture of last abstract command for use with abstractauto
2021-07-12 21:26:00 +01:00
42632e325a
Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
2021-07-12 21:21:16 +01:00
27674be996
Start hacking in a JTAG-DTM
2021-07-12 01:49:32 +01:00
f7b3097ad6
Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
2021-07-11 16:20:39 +01:00
0dce59daaf
Start hacking together a DM
2021-07-11 05:11:19 +01:00
5cc483898d
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
2021-07-10 21:02:18 +01:00
47fa7f4d10
Associated doc updates
2021-07-10 18:53:59 +01:00
63d661af63
Start hacking in debug support to the core -- seems to work as well as before adding debug!
2021-07-10 18:53:48 +01:00
Luke Wren
Vadzim Dambrouski
whitequark