Luke Wren
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887c93dbf0
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Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
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2022-03-02 18:35:16 +00:00 |
Luke Wren
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9ed99d8695
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Use define to guard X-checks, instead of hot comments
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2022-02-24 10:35:16 +00:00 |
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Luke Wren
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bf15b6c49f
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Fix forward reference to net
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2022-01-18 23:02:39 +00:00 |
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Luke Wren
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0a369efc06
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Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
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2021-12-18 15:41:05 +00:00 |
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Luke Wren
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1b0e205f87
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Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
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2021-12-18 14:51:46 +00:00 |
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Luke Wren
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6b8d4913ee
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Remove unnecessary mux of mw_result -> m_result
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2021-12-18 01:34:25 +00:00 |
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Luke Wren
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79fec3a2f5
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Overload mw_result register for capturing AMO read data. Save some LCs.
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2021-12-18 01:24:26 +00:00 |
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Luke Wren
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28b53ef7b5
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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Luke Wren
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7485269ddf
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Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
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2021-12-17 22:36:40 +00:00 |
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Luke Wren
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a35739baf1
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Fix AMO failing to loop on global monitor write fail
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2021-12-17 17:04:22 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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f1cda26bcc
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Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc
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2021-12-12 23:32:01 +00:00 |
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Luke Wren
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25b44d04cf
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Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
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2021-12-12 23:24:25 +00:00 |
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Luke Wren
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88fea7acfa
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Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
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2021-12-12 18:28:23 +00:00 |
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Luke Wren
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9460b3cd04
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Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
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2021-12-11 15:52:34 +00:00 |
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Luke Wren
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3d2c912b4f
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Add test script to make it easier to add software testcases
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2021-12-09 22:25:18 +00:00 |
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Luke Wren
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7d2fa6a049
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Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
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2021-12-09 06:26:31 +00:00 |
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Luke Wren
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116e34df49
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Fix commented out frontend properties which relied on non-constant past reset values
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2021-12-07 20:24:29 +00:00 |
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Luke Wren
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ed22d502fd
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Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend
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2021-12-06 19:28:21 +00:00 |
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Luke Wren
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50d3d5d3b3
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Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed
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2021-12-06 19:27:20 +00:00 |
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Luke Wren
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29c5c8ca7f
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Fix AMO stall falling through when write data phase should proceed to error phase
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2021-12-06 18:28:56 +00:00 |
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Luke Wren
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8bfc089660
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Slightly more strict holdoff of IRQs on AMO
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2021-12-06 18:13:43 +00:00 |
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Luke Wren
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4c532240f8
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Hold off IRQ when AMO is past the point of no return
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2021-12-06 07:45:13 +00:00 |
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Luke Wren
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cc38f46848
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Fix AMO wdata valid left high when entering trap at just the right time
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2021-12-06 07:28:50 +00:00 |
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Luke Wren
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9b9120960d
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Fix missing RAW stall on sc.w succes result. Closing laptop again.
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2021-12-05 01:05:01 +00:00 |
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Luke Wren
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df658d86ff
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First plausibly working AMOs. Add AMOs to instruction timings list
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2021-12-04 23:44:22 +00:00 |
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Luke Wren
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5c098866f2
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Sketch in AMO support
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2021-12-04 20:46:39 +00:00 |
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Luke Wren
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a8933c332d
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Fix illegal issue of pipelined exclusives on the bus, and document correct timings
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2021-12-04 18:23:01 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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607147f280
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Rewrite byte pick/sign-extend logic, preparing to handle more memops
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2021-12-04 12:08:54 +00:00 |
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Luke Wren
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a988adfec8
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Add RISC-V opcodes and memory operation codes for atomics
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2021-12-04 11:16:24 +00:00 |
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Luke Wren
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c8afb4ac33
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Add option for fast high-half multiplies
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2021-11-29 18:48:02 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
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Luke Wren
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ed6b6a3660
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Cleanup order of declaration/use of a couple of wires
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2021-11-25 15:16:59 +00:00 |
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Luke Wren
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e05e9a4109
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Add default_nettype none at top of every file, and default_nettype wire at bottom
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2021-11-23 22:10:39 +00:00 |
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Luke Wren
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0b9b706e81
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Safer logic for load/store blocked by preceding WFI
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2021-11-23 22:01:14 +00:00 |
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Luke Wren
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cc6a6c09ba
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Vaguely implement wfi
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2021-11-05 18:48:42 +00:00 |
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Luke Wren
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cfe16caf41
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Remove some old todos
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2021-09-05 22:20:40 +01:00 |
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Luke Wren
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e9fccffca0
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Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
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2021-09-05 04:45:38 +01:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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8e3dc62b97
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Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
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2021-07-16 20:43:24 +01:00 |
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Luke Wren
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5aca6be572
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Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
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2021-07-16 18:28:30 +01:00 |
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Luke Wren
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307955c810
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Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
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2021-07-13 01:10:55 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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ea5db61582
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Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register)
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2021-05-29 22:52:50 +01:00 |
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Luke Wren
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4b9a3c2c78
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Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
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2021-05-29 19:32:12 +01:00 |
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Luke Wren
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f23ec3f941
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Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
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2021-05-29 18:57:43 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |