8b630d2ac6
Whoops I needed that constant
2022-08-10 01:00:47 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
f47f603595
Doc typos
2022-08-09 00:05:51 +01:00
cd69fcdbbc
Docs: Add date to title page, and rebuild PDF with recent CSR changes
2022-08-08 23:57:20 +01:00
259a402e28
Describe new pmpcfgm0 register
2022-08-08 23:15:28 +01:00
5819f8eb7e
Remove wrong/useless mxr logic in PMP
2022-08-08 18:45:37 +01:00
5894ddf15c
Fix outdated expected output in irq_set_all_with_pri test
2022-08-08 18:44:58 +01:00
92ebbbe95f
Add pmpcfgm0 register: make regions M-mode without locking them
2022-08-08 18:34:55 +01:00
65e3d1c48b
Fix bad IRQ_IMPL_MASK indexing in meipra write
2022-08-08 18:15:38 +01:00
457b5e5f1a
Fix some doc sections which assumed only M-mode was supported
2022-08-08 17:35:39 +01:00
ef927d0d23
Dumb typo
2022-08-08 10:26:36 +01:00
026b529bc5
Fix asm example in docs to set meicontext.clearts when saving
2022-08-07 23:17:39 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
2e3d69e98f
Forgot to add expected output for preemption test
2022-08-07 22:08:50 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
69917ccbbe
Docs: Tweak meicontext with thoughts that came up whilst implementing it
2022-08-07 20:31:14 +01:00
cc12b586ca
Fix implicit net in cpu_1port, this yosys bug is a pain in the ass
2022-08-07 20:30:26 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
054c4a6a9c
Fix reversed pseudocode for ctz/clz
2022-08-02 21:21:44 +01:00
adf81abfdc
Oops, description of shxadd had operands swapped
2022-07-31 17:45:14 +01:00
e76b82e447
More thoughts about interrupts, starting to look plausible
2022-07-31 16:16:16 +01:00
106c4c3d28
Update docs CSR section to reflect addition of U-mode, PMP etc.
2022-07-30 21:19:30 +01:00
797bff81ab
DM: fix any/allnonexistent going low when hasel is set. The hart array mask is in addition to the hart selected by hartsel.
2022-07-30 19:55:22 +01:00
9787c604ad
Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
2022-07-30 17:31:53 +01:00
0567c2c9fe
Two minor DM bugs:
...
- Writes to dmcontrol.resumereq should be ignored if dmcontrol.haltreq is also set
- aarsize and regno should be ignored when command.transfer is not set
2022-07-30 17:22:46 +01:00
c73c09a48a
More thinking about interrupt priorities
2022-07-30 15:42:26 +01:00
7946432d7a
Speculatively update docs with new interrupt array/priority stuff, and sleep register
2022-07-28 01:18:13 +01:00
add19506a5
Oops, bad if block nesting in PMP
2022-07-25 13:09:03 +01:00
ae30d7c0d2
Add instruction pseudocode (no A extension)
2022-07-10 19:16:43 +01:00
956b386a20
Update instruction listings in docs
2022-07-10 05:47:19 +01:00
ee7d8e1947
Bump embench for script fixes/improvements
2022-07-07 18:29:37 +01:00
91be98f2da
Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
2022-07-06 23:53:11 +01:00
9bc72cca08
Update configure line for riscv-gnu-toolchain in readme
2022-07-06 22:41:32 +01:00
5a39d8b7e7
Track minstret and mcycle separately now that the model is cycle-accurate
2022-07-06 13:50:13 +01:00
5dfe5cb62b
Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
2022-07-06 13:49:51 +01:00
b7d9defcf2
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
2022-07-05 03:37:19 +01:00
254350d300
Clean up tie-off of hardwired PMP registers
2022-07-04 14:31:42 +01:00
6e80492723
Typo
2022-07-04 12:09:21 +01:00
27793b25a1
Rebase riscv-tests against upstream, and pick up new semihosting file io test
2022-07-04 00:45:20 +01:00
e44d2e6f9e
Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
2022-07-03 23:34:12 +01:00
cac98568e6
Ignore read data from failed SBA accesses
2022-07-03 20:58:01 +01:00
c7a32c4d00
SBA: fix alignment check using a stale address when the trigger is an sbaddress write. Fix new transfers being allowed to start when sberror or sbbusyerror are set.
2022-07-03 19:02:30 +01:00
ae11d04b10
Add HMASTER output to processor wrappers, to indicate when the bus cycle is driven by SBA rather than the core
2022-07-03 18:02:47 +01:00
b1225c386c
Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
2022-07-03 17:57:03 +01:00
9e15cd3485
Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
2022-07-03 15:30:33 +01:00
d5cd3e0681
Add SBA patch-through to 1-core wrapper.
...
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
2022-07-03 15:17:44 +01:00
d6bef56788
Fix missing byte picking/replication in non-word-aligned SBA transfers
2022-07-03 14:22:12 +01:00
51bc26f8ac
First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
2022-07-03 00:25:47 +01:00
Luke Wren