Luke Wren
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b80b09afe5
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Typo -- fully encode all 128 possible IRQs
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2022-03-15 09:01:55 +00:00 |
Luke Wren
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b0b8703ea4
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Support up to 128 IRQs
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2022-03-13 09:27:43 +00:00 |
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Luke Wren
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887c93dbf0
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Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
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2022-03-02 18:35:16 +00:00 |
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Luke Wren
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96c69d0bb0
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Cut in->out paths on debug halt/resume request
Should be harmless, because in practice these should always be driven from a register
in the DM, but still better to cut the path
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2022-03-01 21:14:49 +00:00 |
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Luke Wren
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5aca1381ac
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Couple of fixups for rvpy which I forgot to commit at some point
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2022-03-01 20:27:18 +00:00 |
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Luke Wren
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8fbffbe133
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Assign full width of fifo_valid in non-reset clause (cosmetic fix)
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2022-02-24 12:00:27 +00:00 |
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Luke Wren
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9ed99d8695
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Use define to guard X-checks, instead of hot comments
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2022-02-24 10:35:16 +00:00 |
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Luke Wren
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bf15b6c49f
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Fix forward reference to net
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2022-01-18 23:02:39 +00:00 |
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Luke Wren
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0a369efc06
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Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
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2021-12-18 15:41:05 +00:00 |
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Luke Wren
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1b0e205f87
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Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
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2021-12-18 14:51:46 +00:00 |
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Luke Wren
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d1b5f83b7a
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Beef up the ULX3S SoC again now that atomics aren't so disastrous for timing
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2021-12-18 02:41:50 +00:00 |
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Luke Wren
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6b8d4913ee
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Remove unnecessary mux of mw_result -> m_result
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2021-12-18 01:34:25 +00:00 |
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Luke Wren
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79fec3a2f5
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Overload mw_result register for capturing AMO read data. Save some LCs.
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2021-12-18 01:24:26 +00:00 |
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Luke Wren
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28b53ef7b5
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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Luke Wren
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7485269ddf
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Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
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2021-12-17 22:36:40 +00:00 |
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Luke Wren
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a35739baf1
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Fix AMO failing to loop on global monitor write fail
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2021-12-17 17:04:22 +00:00 |
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Luke Wren
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a81d129961
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Add exclusives monitor to testbench
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2021-12-17 17:03:35 +00:00 |
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Luke Wren
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5ab60422ad
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Add minimal multicore launch code
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2021-12-17 01:24:11 +00:00 |
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Luke Wren
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01d9617f9c
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Add multicore tb integration file
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2021-12-17 00:41:23 +00:00 |
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Luke Wren
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207566660d
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tb: handle both ports identically. Preparing for dual core
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2021-12-17 00:04:00 +00:00 |
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Luke Wren
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1fa0d4d442
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Create LICENSE
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2021-12-13 23:40:14 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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f1cda26bcc
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Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc
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2021-12-12 23:32:01 +00:00 |
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Luke Wren
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25b44d04cf
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Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
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2021-12-12 23:24:25 +00:00 |
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Luke Wren
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1697192c62
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Fix cycle timing docs for sc.w: 2 cycles if next instruction is RAW-dependent.
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2021-12-12 20:50:26 +00:00 |
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Luke Wren
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88fea7acfa
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Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
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2021-12-12 18:28:23 +00:00 |
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Luke Wren
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719c21fec3
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Add IRQ tests. Disable waves by default in runtests
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2021-12-12 15:53:04 +00:00 |
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Luke Wren
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9fb2af800f
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Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
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2021-12-12 14:58:50 +00:00 |
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Luke Wren
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a232833d81
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Add CSR writable test
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2021-12-12 14:23:34 +00:00 |
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Luke Wren
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8a003dbbed
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Make mcycle/minstret inhibited by default
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2021-12-12 13:55:33 +00:00 |
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Luke Wren
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2bbc3637a2
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Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
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2021-12-12 00:38:30 +00:00 |
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Luke Wren
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7da67a0600
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Similarly for minstret
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2021-12-11 22:25:12 +00:00 |
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Luke Wren
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1b722b5f27
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Add mcycle test, fix incorrect description of mcycle in docs
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2021-12-11 21:21:31 +00:00 |
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Luke Wren
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93eca19aeb
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Add test for lr/sc RAW stalls
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2021-12-11 19:16:41 +00:00 |
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Luke Wren
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763a5cd364
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Add test for readability of all implemented CSRs
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2021-12-11 17:50:12 +00:00 |
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Luke Wren
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7b1da32af1
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Move expected_output into tests inline
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2021-12-11 16:58:25 +00:00 |
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Luke Wren
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9460b3cd04
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Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
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2021-12-11 15:52:34 +00:00 |
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Luke Wren
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f64f44f7af
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Add test for identification CSRs vs expected values
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2021-12-11 13:26:59 +00:00 |
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Luke Wren
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4066e941ef
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Fix sim cmdline in bitmanip-random tests
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2021-12-11 13:13:21 +00:00 |
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Luke Wren
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3fe0d92d41
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Add load/store alignment testcases
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2021-12-11 12:53:37 +00:00 |
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Luke Wren
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c90727b05a
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Remove padding after vector table in init.S
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2021-12-11 12:22:23 +00:00 |
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Luke Wren
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6076eba61f
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Add run_all script under riscv-compliance
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2021-12-11 12:08:53 +00:00 |
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Luke Wren
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52d58fdee4
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Add keep wires for debug port on bus compliance tb
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2021-12-11 12:06:10 +00:00 |
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Luke Wren
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6edfbfae8b
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Add ebreak size/alignment test
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2021-12-11 11:17:24 +00:00 |
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Luke Wren
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cccc32fe16
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Update instructions for running hello world under debugger
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2021-12-11 10:25:29 +00:00 |
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Luke Wren
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abe1769929
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Add instruction access fault testcase
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2021-12-11 09:54:00 +00:00 |
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Luke Wren
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933f2cd65c
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Fix remaining fallout from tb args change
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2021-12-11 09:53:39 +00:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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fadb9601de
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Illegal instruction test
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2021-12-10 00:11:18 +00:00 |
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Luke Wren
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3d2c912b4f
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Add test script to make it easier to add software testcases
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2021-12-09 22:25:18 +00:00 |