Luke Wren
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9dd091b7b5
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Doh typo
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2021-08-21 09:06:20 +01:00 |
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Luke Wren
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b99e5b8a67
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Convert timer to serial for smaller area. Rather untested
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2021-08-20 22:27:15 +01:00 |
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Luke Wren
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4aba165166
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First pass at a 64-bit system timer
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2021-08-20 21:49:05 +01:00 |
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Luke Wren
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8263ee3a5d
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Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
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2021-07-24 15:31:33 +01:00 |
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Luke Wren
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70a44d9681
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Small code cleanup
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2021-07-24 10:08:27 +01:00 |
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Luke Wren
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155d3ba554
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Tie off 1 or 2 LSBs of DPC depending on IALIGN
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2021-07-23 23:09:03 +01:00 |
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Luke Wren
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115cb2c50f
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Tweaks to example soc configuration
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2021-07-23 23:08:23 +01:00 |
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Luke Wren
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279e4b4f29
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Implement mstatush as hardwired-0, as required by priv-1.12
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2021-07-23 21:52:01 +01:00 |
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Luke Wren
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2ae30183aa
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Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
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2021-07-23 18:32:47 +01:00 |
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Luke Wren
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8ceae7e9e6
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Start hacking on ECP5 JTAG DTM
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2021-07-23 00:36:55 +01:00 |
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Luke Wren
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41477ce479
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Extract DTM bus/control logic from the JTAG-related parts
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2021-07-22 19:26:25 +01:00 |
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Luke Wren
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8cdde82248
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Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
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2021-07-20 00:13:26 +01:00 |
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Luke Wren
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7d24f42da9
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Oops, properly fix platform IRQ mcause numbers
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2021-07-19 09:32:59 +01:00 |
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Luke Wren
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65fb62901e
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Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
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2021-07-19 00:19:56 +01:00 |
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Luke Wren
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70443fa557
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Disable shifting of MIE/MPIE stack when in or entering debug mode
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2021-07-18 21:14:11 +01:00 |
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Luke Wren
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d30fc46f5b
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Fix IRQ mcause not being set correctly when vectoring is disabled
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2021-07-18 20:44:39 +01:00 |
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Luke Wren
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e95b465e26
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Typo in address of mcountinhibit!
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2021-07-17 19:27:01 +01:00 |
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Luke Wren
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d9300ee127
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Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry
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2021-07-17 19:26:45 +01:00 |
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Luke Wren
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5deff12f95
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DM: don't report as running/halted in dmstatus if unavailable.
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2021-07-17 16:46:39 +01:00 |
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Luke Wren
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ab0b4a04f0
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Also support progbuf in abstractauto.
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2021-07-17 15:08:00 +01:00 |
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Luke Wren
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8e3dc62b97
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Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
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2021-07-16 20:43:24 +01:00 |
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Luke Wren
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5aca6be572
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Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
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2021-07-16 18:28:30 +01:00 |
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Luke Wren
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ce5152a4f4
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Implement HALTSUM0 and HALTSUM1 registers
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2021-07-16 17:58:28 +01:00 |
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Luke Wren
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011008efd1
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Fix detection of exception-like vs IRQ-like halt/trap entries
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2021-07-15 19:41:35 +01:00 |
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Luke Wren
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71ec9fa283
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Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
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2021-07-14 20:39:51 +01:00 |
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Luke Wren
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f4952ab66d
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Add simple example SoC, hangs nextpnr for some reason!
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2021-07-13 03:40:06 +01:00 |
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Luke Wren
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307955c810
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Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
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2021-07-13 01:10:55 +01:00 |
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Luke Wren
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93c7039ea1
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Sync doc updates
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2021-07-12 22:13:31 +01:00 |
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Luke Wren
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4b650ac437
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DM: add missing w1c to abstract cmderr, add capture of last abstract command for use with abstractauto
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2021-07-12 21:26:00 +01:00 |
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Luke Wren
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42632e325a
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Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
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2021-07-12 21:21:16 +01:00 |
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Luke Wren
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27674be996
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Start hacking in a JTAG-DTM
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2021-07-12 01:49:32 +01:00 |
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Luke Wren
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f7b3097ad6
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Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
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2021-07-11 16:20:39 +01:00 |
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Luke Wren
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0dce59daaf
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Start hacking together a DM
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2021-07-11 05:11:19 +01:00 |
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Luke Wren
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5cc483898d
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Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
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2021-07-10 21:02:18 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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83244c6651
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Add Read ID command to UART DTM
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2021-07-10 16:14:35 +01:00 |
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Luke Wren
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3312ea7022
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Add draft UART DTM
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2021-07-08 17:57:46 +01:00 |
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Luke Wren
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6a38fc33a6
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Allow MHARTID to be configured at instantiation
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2021-07-07 16:08:08 +01:00 |
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Luke Wren
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278dc8b6a2
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meie0 default to all-zeroes
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2021-06-04 07:37:02 +01:00 |
Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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12851d3742
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Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
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2021-05-30 19:52:46 +01:00 |
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Luke Wren
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cec5dc4e3b
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Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters
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2021-05-30 19:20:53 +01:00 |
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Luke Wren
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565b76672a
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Make MVENDORID/MARCHID/MIMPID configurable
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2021-05-30 18:42:43 +01:00 |
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Luke Wren
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2330b84b73
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Use .f for riscv-formal tb dependencies, small reshuffling of directories
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2021-05-30 09:44:57 +01:00 |
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Luke Wren
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ad8f251ba2
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RVFI wrapper: use proper bus assumptions. RVFI monitor: don't mark instruction which is aligned with IRQ as invalid, because the IRQ entry is notionally behind it
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2021-05-29 23:24:02 +01:00 |
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Luke Wren
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ea5db61582
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Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register)
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2021-05-29 22:52:50 +01:00 |
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Luke Wren
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4b9a3c2c78
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Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
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2021-05-29 19:32:12 +01:00 |
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Luke Wren
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f23ec3f941
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Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
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2021-05-29 18:57:43 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |