3a747e1dde
Disable zcmp in multilib-gen-gen for now, as it is still not supported in latest binutils release
2024-06-01 18:24:06 +01:00
b883be3c20
Update multilib-gen-gen for GCC14 extensions: Zicond, Zcmp, Zcb. Hopefully handle the Zca vs C thing gracefully.
2024-06-01 18:01:09 +01:00
d4212f8976
Limit multilib-gen-gen to more-useful ISA combinations
2023-11-30 05:32:39 +00:00
10a6c2616a
Add utility script for generating long multilib configure lines when building riscv-gnu-toolchain
2023-11-04 12:27:31 +00:00
817a1ddfcb
Update src_only_app.mk to make overriding TB executable path easier
...
(e.g. for running tests against rvcpp or an external simulator
2023-11-04 12:16:39 +00:00
2f6e98335f
Add two new tests for IRQs-over-Zcmp, and fix a bug they found:
...
Interrupting the PC-setting step of a cm.popret (only) can sample the return target
as the exception return PC, which will cause the stack pointer adjust to be skipped
when returning from the IRQ. Fix this by making the PC-setting step uninterruptible
(note the PC-setting step is the instruction we execute first out of the group
of instructions specified in the Zc spec as being atomic wrt interrupts. This
does not itself imply that the PC-setting step is uninterruptible, it just
requires that when the PC-setting step retires, all following steps also retire.
However this is not sufficient given the special case logic that allows the jr
ra PC-setting step to execute before the final stack adjust as an optimisation.)
2023-11-03 21:12:21 +00:00
8b301c5692
Silence useless linker rwx warning
2023-11-03 20:09:02 +00:00
5aee830ac0
Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
...
(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
64d9f4a111
Add tests for execution of mret and wfi in U mode
2022-05-24 22:14:20 +01:00
a81d129961
Add exclusives monitor to testbench
2021-12-17 17:03:35 +00:00
5ab60422ad
Add minimal multicore launch code
2021-12-17 01:24:11 +00:00
9fb2af800f
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
2021-12-12 14:58:50 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
763a5cd364
Add test for readability of all implemented CSRs
2021-12-11 17:50:12 +00:00
c90727b05a
Remove padding after vector table in init.S
2021-12-11 12:22:23 +00:00
abe1769929
Add instruction access fault testcase
2021-12-11 09:54:00 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
ac9285846f
Timer struct in IO header
2021-12-06 17:16:21 +00:00
c5d6be24f3
Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
2021-12-04 14:06:48 +00:00
ba248c832a
init.S: also print out mcause when trapping an unhandled exception
2021-11-29 18:49:37 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
be79a611e1
Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.
2021-06-04 09:19:18 +01:00
c03bc2efb5
Update init.S for new IRQ functionality
2021-06-04 08:16:54 +01:00
12851d3742
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
2021-05-30 19:52:46 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
Luke Wren