6 Commits

Author	SHA1	Message	Date
Colin	c6d2b351df	Change clock from 12 to 25.	2025-04-06 19:47:55 +08:00
Colin	3255e9e952	Pass ECP5 fpga and jlink debug core.	2025-04-02 10:41:27 +08:00
Colin	bf0e102e90	Add synth support.	2025-03-31 19:10:52 +08:00
Colin	2e649e2c86	Add softuart to soc_cxxrtl test.	2025-03-30 18:36:35 +08:00
Colin	5ec810907e	Refine soc_cxxrtl and pass demo.	2025-03-27 16:02:09 +08:00
Colin	616da81d63	Add soc_cxxrtl simulation.	2025-03-26 16:28:09 +08:00