Luke Wren
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ce5152a4f4
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Implement HALTSUM0 and HALTSUM1 registers
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2021-07-16 17:58:28 +01:00 |
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Luke Wren
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011008efd1
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Fix detection of exception-like vs IRQ-like halt/trap entries
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2021-07-15 19:41:35 +01:00 |
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Luke Wren
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71ec9fa283
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Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
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2021-07-14 20:39:51 +01:00 |
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Luke Wren
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f4952ab66d
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Add simple example SoC, hangs nextpnr for some reason!
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2021-07-13 03:40:06 +01:00 |
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Luke Wren
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307955c810
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Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
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2021-07-13 01:10:55 +01:00 |
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Luke Wren
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93c7039ea1
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Sync doc updates
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2021-07-12 22:13:31 +01:00 |
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Luke Wren
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4b650ac437
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DM: add missing w1c to abstract cmderr, add capture of last abstract command for use with abstractauto
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2021-07-12 21:26:00 +01:00 |
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Luke Wren
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42632e325a
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Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
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2021-07-12 21:21:16 +01:00 |
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Luke Wren
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27674be996
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Start hacking in a JTAG-DTM
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2021-07-12 01:49:32 +01:00 |
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Luke Wren
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f7b3097ad6
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Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
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2021-07-11 16:20:39 +01:00 |
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Luke Wren
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0dce59daaf
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Start hacking together a DM
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2021-07-11 05:11:19 +01:00 |
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Luke Wren
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5cc483898d
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Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
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2021-07-10 21:02:18 +01:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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83244c6651
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Add Read ID command to UART DTM
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2021-07-10 16:14:35 +01:00 |
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Luke Wren
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3312ea7022
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Add draft UART DTM
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2021-07-08 17:57:46 +01:00 |
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Luke Wren
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6a38fc33a6
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Allow MHARTID to be configured at instantiation
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2021-07-07 16:08:08 +01:00 |
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Luke Wren
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278dc8b6a2
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meie0 default to all-zeroes
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2021-06-04 07:37:02 +01:00 |
Luke Wren
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af684c4e82
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Some cleanup; correctly decode 16-bit EBREAK
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2021-06-03 20:03:43 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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12851d3742
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Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
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2021-05-30 19:52:46 +01:00 |
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Luke Wren
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cec5dc4e3b
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Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters
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2021-05-30 19:20:53 +01:00 |
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Luke Wren
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565b76672a
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Make MVENDORID/MARCHID/MIMPID configurable
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2021-05-30 18:42:43 +01:00 |
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Luke Wren
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2330b84b73
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Use .f for riscv-formal tb dependencies, small reshuffling of directories
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2021-05-30 09:44:57 +01:00 |
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Luke Wren
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ad8f251ba2
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RVFI wrapper: use proper bus assumptions. RVFI monitor: don't mark instruction which is aligned with IRQ as invalid, because the IRQ entry is notionally behind it
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2021-05-29 23:24:02 +01:00 |
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Luke Wren
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ea5db61582
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Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register)
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2021-05-29 22:52:50 +01:00 |
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Luke Wren
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4b9a3c2c78
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Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
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2021-05-29 19:32:12 +01:00 |
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Luke Wren
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f23ec3f941
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Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
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2021-05-29 18:57:43 +01:00 |
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Luke Wren
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65075df0e5
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More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
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2021-05-29 18:00:43 +01:00 |
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Luke Wren
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1b252d4bda
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Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
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2021-05-23 11:59:46 +01:00 |
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Luke Wren
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5e61c9f9ac
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Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
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2021-05-23 09:12:50 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |
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Luke Wren
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7a3ce494e4
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Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
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2021-05-23 06:40:44 +01:00 |
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Luke Wren
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dec78a728d
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Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
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2021-05-22 15:35:52 +01:00 |
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Luke Wren
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08e986912c
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Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
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2021-05-22 11:18:56 +01:00 |
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Luke Wren
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6692c1f26d
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Fix premature taking of branches with RAW data dependencies on the previous instruction
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2021-05-22 10:18:47 +01:00 |
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Luke Wren
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cc6f590f2e
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Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
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2021-05-22 10:16:02 +01:00 |
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Luke Wren
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692abbad8b
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Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
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2021-05-22 07:55:13 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |
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Luke Wren
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5de4f01aae
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Change how constants are plumbed through the hierarchy. Some small cleanups of variable declaration order etc
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2021-05-21 03:23:44 +01:00 |
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Luke Wren
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6dad4e20bb
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Import from hazard5 9743a1b
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2021-05-21 02:34:16 +01:00 |