d3667769d2
Arrange for address buses to be 0 when processor is held in reset
2022-10-08 16:50:58 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
96e55a5446
Replace localparams with defines in rv_opcodes.vh, to avoid slightly dubious localparam to casez Z-propagation
2022-08-20 16:22:04 +01:00
d299a3ca4e
More width tweaks
2022-08-20 16:11:58 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
...
and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
173f5dba9d
Fix jump target being unstable during a CIR-locked branch-to-self on a partial predicted branch match, due to the addr_is_regoffs decode not being tied off.
2022-06-25 20:07:43 +01:00
31efd07042
Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)
2022-06-25 11:32:56 +01:00
979e80be99
Attempt to fix fetch mismatch caused by jumping halfway into a 32-bit
...
instruction that precedes a taken branch.
The bookkeeping in the frontend has been tightened up so that the entire
branch instruction, and nothing but the branch instruction, is marked as a
taken branch. This required some extra state, e.g. remembering the size of
the taken branch instruction, but saved an incrementer on the BTB source
address value.
2022-06-24 19:58:21 +01:00
d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
f8aad6d2f3
Fix some bugs, too tired to list them, look at the diff
2022-06-15 04:05:31 +01:00
0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
26d54d0023
Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
2022-06-12 21:01:39 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
51750eb81d
Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
2022-05-24 21:12:44 +01:00
210dbeae64
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
43e0b1d16a
Implement Zbkb (untested)
2022-05-06 17:36:25 +01:00
2c8f3974d0
Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
2022-04-09 13:49:16 +01:00
887c93dbf0
Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
2022-03-02 18:35:16 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
7485269ddf
Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
2021-12-17 22:36:40 +00:00
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
7d2fa6a049
Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
2021-12-09 06:26:31 +00:00
260491405a
Fix atomic instructions not asserting decode error when A extension is disabled
2021-12-06 07:28:50 +00:00
12c79c0b41
Fix feature-flag for Zbs instructions in decoder
2021-12-05 02:05:35 +00:00
5c098866f2
Sketch in AMO support
2021-12-04 20:46:39 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
58c20a39d0
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
2021-11-25 23:30:35 +00:00
cc6a6c09ba
Vaguely implement wfi
2021-11-05 18:48:42 +00:00
d03a82a826
Add instruction fetch faults
2021-09-04 02:57:39 +01:00
63d661af63
Start hacking in debug support to the core -- seems to work as well as before adding debug!
2021-07-10 18:53:48 +01:00
af684c4e82
Some cleanup; correctly decode 16-bit EBREAK
2021-06-03 20:03:43 +01:00
4b9a3c2c78
Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
2021-05-29 19:32:12 +01:00
65075df0e5
More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
2021-05-29 18:00:43 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
5e61c9f9ac
Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
2021-05-23 09:12:50 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
7a3ce494e4
Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
2021-05-23 06:40:44 +01:00
dec78a728d
Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
2021-05-22 15:35:52 +01:00
692abbad8b
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
2021-05-22 07:55:13 +01:00
844fa8f97f
Rename hazard5 -> hazard3
2021-05-21 03:46:29 +01:00
Luke Wren
Luke Wren