4d14203586
Update riscv-tests fork for crash loop debug test
2021-11-23 21:58:39 +00:00
c1f17b0b23
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
2021-11-06 09:59:27 +00:00
375a6d60b7
Correct mnemonic when logging unsigned sltiu instruction
2021-10-08 12:02:37 +01:00
6fcc74a043
Add some instructions to Readme
2021-07-24 11:53:08 +01:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
c14960ee1b
Add mtime/mtimecmp to openocd testbench
2021-07-22 17:31:26 +01:00
5d2a562f65
Just use read_verilog; write_cxxrtl when building tb_cxxrtl
2021-07-22 17:30:30 +01:00
c56c75e14b
More dicking with yosys cmd for tb_cxxrtl;
...
Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
2021-07-18 16:46:00 +01:00
12bf9bb570
Make CXXRTL testbench ~25% faster
2021-07-18 16:04:19 +01:00
2618ae0c07
Double-step() after clock posedge to workaround CXXRTL port propagation issue
2021-07-18 16:03:53 +01:00
ce5cc1f150
oops, bounds checking on free-running tb_cxxrtl
2021-07-18 15:20:25 +01:00
8014239d47
openocd tb: report AHB error response when processor accesses outside of RAM/IO
2021-07-17 19:26:05 +01:00
ab0b4a04f0
Also support progbuf in abstractauto.
2021-07-17 15:08:00 +01:00
62822b2e1d
Couple of usability improvements for openocd testbench
2021-07-15 19:42:49 +01:00
9643a57ba9
Slightly less braindead TCP interactions for openocd JTAG bitbang testbench, much more interactive now
2021-07-14 19:20:27 +01:00
307955c810
Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
2021-07-13 01:10:55 +01:00
42632e325a
Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
2021-07-12 21:21:16 +01:00
f7b3097ad6
Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
2021-07-11 16:20:39 +01:00
5cc483898d
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
2021-07-10 21:02:18 +01:00
58a6b8b4c8
Add 32IM testlist
2021-06-05 12:03:05 +01:00
be79a611e1
Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.
2021-06-04 09:19:18 +01:00
c03bc2efb5
Update init.S for new IRQ functionality
2021-06-04 08:16:54 +01:00
12851d3742
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
2021-05-30 19:52:46 +01:00
12205f12c7
Add instruction fetch match check
2021-05-30 11:22:36 +01:00
16dc905dce
Add simple formal bus properties check
2021-05-30 10:19:42 +01:00
2330b84b73
Use .f for riscv-formal tb dependencies, small reshuffling of directories
2021-05-30 09:44:57 +01:00
089bcc7c43
Typo
2021-05-29 23:24:18 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
08e986912c
Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
2021-05-22 11:18:56 +01:00
cc6f590f2e
Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
2021-05-22 10:16:02 +01:00
692abbad8b
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
2021-05-22 07:55:13 +01:00
844fa8f97f
Rename hazard5 -> hazard3
2021-05-21 03:46:29 +01:00
6dad4e20bb
Import from hazard5 9743a1b
2021-05-21 02:34:16 +01:00
Luke Wren
Richard-Gordon
whitequark