Luke Wren
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c5e85dea4c
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Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
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Luke Wren
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c8afb4ac33
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Add option for fast high-half multiplies
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2021-11-29 18:48:02 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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1aa9dbcddd
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Fix comment typo in APB clock crossing
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2021-11-28 17:40:57 +00:00 |
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Luke Wren
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e7466ae4be
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Move DM data0 CSR into the M-custom space, and document this
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2021-11-28 15:52:52 +00:00 |
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Luke Wren
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76172cdade
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Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
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2021-11-28 06:33:35 +00:00 |
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Luke Wren
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800b21d2f5
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Remove event feedback path (not logical path) in priority encoder
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2021-11-28 02:19:01 +00:00 |
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Luke Wren
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14a4f1a281
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Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
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2021-11-27 17:19:41 +00:00 |
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Luke Wren
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5d093487b7
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Update README
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2021-11-26 23:33:46 +00:00 |
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Luke Wren
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1bb7e33b69
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Fix alignment of heap_ptr in init.S. Small ALU cleanup
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2021-11-26 02:59:50 +00:00 |
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Luke Wren
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8bcec11c80
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Couple more silly mistakes
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2021-11-26 01:30:13 +00:00 |
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Luke Wren
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41eeb90c7d
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Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
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2021-11-26 01:29:47 +00:00 |
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Luke Wren
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998f3fdeb7
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Clean up silly mistakes
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2021-11-26 00:55:57 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
Luke Wren
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ed6b6a3660
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Cleanup order of declaration/use of a couple of wires
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2021-11-25 15:16:59 +00:00 |
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Luke Wren
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49462a8642
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Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
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2021-11-23 22:11:50 +00:00 |
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Luke Wren
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e05e9a4109
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Add default_nettype none at top of every file, and default_nettype wire at bottom
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2021-11-23 22:10:39 +00:00 |
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Luke Wren
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0b9b706e81
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Safer logic for load/store blocked by preceding WFI
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2021-11-23 22:01:14 +00:00 |
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Luke Wren
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cc6a6c09ba
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Vaguely implement wfi
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2021-11-05 18:48:42 +00:00 |
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Luke Wren
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cfe16caf41
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Remove some old todos
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2021-09-05 22:20:40 +01:00 |
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Luke Wren
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e9fccffca0
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Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
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2021-09-05 04:45:38 +01:00 |
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Luke Wren
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65bfca5fdf
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Fix latent bug with asynchronous debug entry during stalled load/store address phase
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2021-09-04 07:49:29 +01:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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e16ae06cb5
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Clean up timer
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2021-08-21 17:03:32 +01:00 |
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Luke Wren
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9dd091b7b5
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Doh typo
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2021-08-21 09:06:20 +01:00 |
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Luke Wren
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b99e5b8a67
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Convert timer to serial for smaller area. Rather untested
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2021-08-20 22:27:15 +01:00 |
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Luke Wren
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4aba165166
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First pass at a 64-bit system timer
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2021-08-20 21:49:05 +01:00 |
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Luke Wren
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8263ee3a5d
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Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
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2021-07-24 15:31:33 +01:00 |
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Luke Wren
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70a44d9681
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Small code cleanup
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2021-07-24 10:08:27 +01:00 |
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Luke Wren
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155d3ba554
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Tie off 1 or 2 LSBs of DPC depending on IALIGN
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2021-07-23 23:09:03 +01:00 |
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Luke Wren
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115cb2c50f
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Tweaks to example soc configuration
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2021-07-23 23:08:23 +01:00 |
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Luke Wren
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279e4b4f29
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Implement mstatush as hardwired-0, as required by priv-1.12
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2021-07-23 21:52:01 +01:00 |
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Luke Wren
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2ae30183aa
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Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
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2021-07-23 18:32:47 +01:00 |
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Luke Wren
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8ceae7e9e6
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Start hacking on ECP5 JTAG DTM
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2021-07-23 00:36:55 +01:00 |
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Luke Wren
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41477ce479
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Extract DTM bus/control logic from the JTAG-related parts
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2021-07-22 19:26:25 +01:00 |
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Luke Wren
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8cdde82248
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Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
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2021-07-20 00:13:26 +01:00 |
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Luke Wren
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7d24f42da9
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Oops, properly fix platform IRQ mcause numbers
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2021-07-19 09:32:59 +01:00 |
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Luke Wren
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65fb62901e
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Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
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2021-07-19 00:19:56 +01:00 |
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Luke Wren
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70443fa557
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Disable shifting of MIE/MPIE stack when in or entering debug mode
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2021-07-18 21:14:11 +01:00 |
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Luke Wren
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d30fc46f5b
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Fix IRQ mcause not being set correctly when vectoring is disabled
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2021-07-18 20:44:39 +01:00 |
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Luke Wren
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e95b465e26
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Typo in address of mcountinhibit!
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2021-07-17 19:27:01 +01:00 |
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Luke Wren
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d9300ee127
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Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry
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2021-07-17 19:26:45 +01:00 |
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Luke Wren
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5deff12f95
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DM: don't report as running/halted in dmstatus if unavailable.
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2021-07-17 16:46:39 +01:00 |
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Luke Wren
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ab0b4a04f0
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Also support progbuf in abstractauto.
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2021-07-17 15:08:00 +01:00 |
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Luke Wren
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8e3dc62b97
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Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
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2021-07-16 20:43:24 +01:00 |
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Luke Wren
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5aca6be572
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Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
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2021-07-16 18:28:30 +01:00 |
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Luke Wren
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ce5152a4f4
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Implement HALTSUM0 and HALTSUM1 registers
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2021-07-16 17:58:28 +01:00 |
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Luke Wren
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011008efd1
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Fix detection of exception-like vs IRQ-like halt/trap entries
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2021-07-15 19:41:35 +01:00 |
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Luke Wren
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71ec9fa283
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Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
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2021-07-14 20:39:51 +01:00 |
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Luke Wren
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f4952ab66d
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Add simple example SoC, hangs nextpnr for some reason!
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2021-07-13 03:40:06 +01:00 |