f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
d62861159f
First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
2022-05-24 16:17:54 +01:00
f849517202
Split CSR addresses into separate header file
2022-05-23 15:54:37 +01:00
df0fd536eb
Fix IRQ priority to match the priv spec
2022-05-23 12:56:37 +01:00
c4e81922da
Don't store bit 1 of mepc on non-RVC implementations
2022-05-23 12:27:07 +01:00
b80b09afe5
Typo -- fully encode all 128 possible IRQs
2022-03-15 09:01:55 +00:00
b0b8703ea4
Support up to 128 IRQs
2022-03-13 09:27:43 +00:00
96c69d0bb0
Cut in->out paths on debug halt/resume request
...
Should be harmless, because in practice these should always be driven from a register
in the DM, but still better to cut the path
2022-03-01 21:14:49 +00:00
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
25b44d04cf
Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
2021-12-12 23:24:25 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
2bbc3637a2
Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
2021-12-12 00:38:30 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
c5e85dea4c
Add mconfigptr CSR
2021-12-01 03:25:56 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
76172cdade
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
2021-11-28 06:33:35 +00:00
cc6a6c09ba
Vaguely implement wfi
2021-11-05 18:48:42 +00:00
cfe16caf41
Remove some old todos
2021-09-05 22:20:40 +01:00
e9fccffca0
Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
2021-09-05 04:45:38 +01:00
65bfca5fdf
Fix latent bug with asynchronous debug entry during stalled load/store address phase
2021-09-04 07:49:29 +01:00
8263ee3a5d
Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
2021-07-24 15:31:33 +01:00
155d3ba554
Tie off 1 or 2 LSBs of DPC depending on IALIGN
2021-07-23 23:09:03 +01:00
279e4b4f29
Implement mstatush as hardwired-0, as required by priv-1.12
2021-07-23 21:52:01 +01:00
7d24f42da9
Oops, properly fix platform IRQ mcause numbers
2021-07-19 09:32:59 +01:00
65fb62901e
Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
2021-07-19 00:19:56 +01:00
70443fa557
Disable shifting of MIE/MPIE stack when in or entering debug mode
2021-07-18 21:14:11 +01:00
d30fc46f5b
Fix IRQ mcause not being set correctly when vectoring is disabled
2021-07-18 20:44:39 +01:00
e95b465e26
Typo in address of mcountinhibit!
2021-07-17 19:27:01 +01:00
8e3dc62b97
Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
2021-07-16 20:43:24 +01:00
5aca6be572
Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
2021-07-16 18:28:30 +01:00
011008efd1
Fix detection of exception-like vs IRQ-like halt/trap entries
2021-07-15 19:41:35 +01:00
71ec9fa283
Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
2021-07-14 20:39:51 +01:00
5cc483898d
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
2021-07-10 21:02:18 +01:00
63d661af63
Start hacking in debug support to the core -- seems to work as well as before adding debug!
2021-07-10 18:53:48 +01:00
6a38fc33a6
Allow MHARTID to be configured at instantiation
2021-07-07 16:08:08 +01:00
278dc8b6a2
meie0 default to all-zeroes
2021-06-04 07:37:02 +01:00
af684c4e82
Some cleanup; correctly decode 16-bit EBREAK
2021-06-03 20:03:43 +01:00
5f8d217395
Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
2021-05-31 17:54:12 +01:00
12851d3742
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
2021-05-30 19:52:46 +01:00
cec5dc4e3b
Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters
2021-05-30 19:20:53 +01:00
565b76672a
Make MVENDORID/MARCHID/MIMPID configurable
2021-05-30 18:42:43 +01:00
f23ec3f941
Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
2021-05-29 18:57:43 +01:00
65075df0e5
More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
2021-05-29 18:00:43 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
844fa8f97f
Rename hazard5 -> hazard3
2021-05-21 03:46:29 +01:00
Luke Wren
Luke Wren