fef6d80fd4tcontrol.mpte is not supposed to change on trap exit, unlike mstatus.mpie
Luke Wren
2022-08-23 00:19:56 +0100
9e11c0e5a8Fix tdata1.dmode being writable from M-mode
Luke Wren
2022-08-23 00:08:17 +0100
04f138ae0eFix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
Luke Wren
2022-08-23 00:05:03 +0100
49c2edeff8Avoid reserved keyword
Luke Wren
2022-08-22 10:26:20 +0100
53902a901bFix bad rdata width for tdata1 (which also caused the trigger type to appear as legacy SiFive, oops)
Luke Wren
2022-08-22 09:47:19 +0100
f9dafa3867Update readme
Luke Wren
2022-08-22 09:25:37 +0100
b90d12efedCSRs: avoid use of wdata_update in rdata for meicontext, which the SMT2 backend sees as a loop.
Luke Wren
2022-08-22 09:18:57 +0100
ba775563d5Fix suspicious gating of jump request
Luke Wren
2022-08-22 09:10:12 +0100
6e2076268cUpdate CSR readability/writability tests for new CSRs
Luke Wren
2022-08-22 08:50:57 +0100
6e3799eed0First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
Luke Wren
2022-08-22 08:45:06 +0100
5d6b5a80b0Standardise on ifndef YOSYS around default_nettype wire
Luke Wren
2022-08-21 13:22:55 +0100
4c098d76a7Fix some whitespace issues, and avoid redefinition of RVOPC macros
Luke Wren
2022-08-21 13:09:28 +0100
b994674c5aCleanup to avoid negative array index (legal but causes whinging)
Luke Wren
2022-08-20 18:13:45 +0100
3b7cd9bc96Cleanup some unused signals
Luke Wren
2022-08-20 16:44:39 +0100
96e55a5446Replace localparams with defines in rv_opcodes.vh, to avoid slightly dubious localparam to casez Z-propagation
Luke Wren
2022-08-20 16:22:04 +0100
d299a3ca4eMore width tweaks
Luke Wren
2022-08-20 16:11:58 +0100
bc274867c0More width mismatch fixes
Luke Wren
2022-08-20 15:27:14 +0100
dbe9a7824aCleanup of some width mismatches in instruction decompress
Luke Wren
2022-08-20 14:58:41 +0100
276830ecb6Fix missing default assignment of i_m in PMP decode
Luke Wren
2022-08-16 09:23:42 +0100
65daa739c4.gitignore
Luke Wren
2022-08-16 09:21:14 +0100
be05dc32d4Oops, typo in update of new pmpcfg_m field
Luke Wren
2022-08-11 20:46:32 +0100
8b630d2ac6Whoops I needed that constant
Luke Wren
2022-08-10 01:00:47 +0100
64dc31244eAdd top/bottom-half IRQ test
Luke Wren
2022-08-10 00:09:13 +0100
a44ff9b6f1Add test for IRQ force array
Luke Wren
2022-08-09 23:38:14 +0100
f47f603595Doc typos
Luke Wren
2022-08-09 00:04:30 +0100
cd69fcdbbcDocs: Add date to title page, and rebuild PDF with recent CSR changes
Luke Wren
2022-08-08 23:54:05 +0100
259a402e28Describe new pmpcfgm0 register
Luke Wren
2022-08-08 23:08:31 +0100
5819f8eb7eRemove wrong/useless mxr logic in PMP
Luke Wren
2022-08-08 18:45:37 +0100
5894ddf15cFix outdated expected output in irq_set_all_with_pri test
Luke Wren
2022-08-08 18:44:58 +0100
92ebbbe95fAdd pmpcfgm0 register: make regions M-mode without locking them
Luke Wren
2022-08-08 18:34:55 +0100
65e3d1c48bFix bad IRQ_IMPL_MASK indexing in meipra write
Luke Wren
2022-08-08 17:38:41 +0100
457b5e5f1aFix some doc sections which assumed only M-mode was supported
Luke Wren
2022-08-08 17:35:39 +0100
ef927d0d23Dumb typo
Luke Wren
2022-08-08 10:26:36 +0100
026b529bc5Fix asm example in docs to set meicontext.clearts when saving
Luke Wren
2022-08-07 23:17:39 +0100
ad5fd24772- Fix signal named priority, which is a keyword in SV - Fix incorrect HIGHEST_WINS behaviour in one-hot selector - Add test for asserting 32 IRQs at 16 priorities at once - Add an entry counter to the soft dispatch code so tests can check the number of times hardware entered the vector
Luke Wren
2022-08-07 23:17:03 +0100
2e3d69e98fForgot to add expected output for preemption test
Luke Wren
2022-08-07 22:08:50 +0100
5e72ec8941Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
Luke Wren
2022-08-07 22:04:42 +0100
15cb21ae43First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
Luke Wren
2022-08-07 20:51:12 +0100
69917ccbbeDocs: Tweak meicontext with thoughts that came up whilst implementing it
Luke Wren
2022-08-07 20:31:09 +0100
cc12b586caFix implicit net in cpu_1port, this yosys bug is a pain in the ass
Luke Wren
2022-08-07 20:30:26 +0100
185194973fAdd a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
Luke Wren
2022-08-06 23:02:08 +0100
054c4a6a9cFix reversed pseudocode for ctz/clz
Luke Wren
2022-08-02 21:21:44 +0100
adf81abfdcOops, description of shxadd had operands swapped
Luke Wren
2022-07-31 17:45:14 +0100
e76b82e447More thoughts about interrupts, starting to look plausible
Luke Wren
2022-07-31 16:16:16 +0100
106c4c3d28Update docs CSR section to reflect addition of U-mode, PMP etc.
Luke Wren
2022-07-30 21:19:30 +0100
797bff81abDM: fix any/allnonexistent going low when hasel is set. The hart array mask is in addition to the hart selected by hartsel.
Luke Wren
2022-07-30 19:55:22 +0100
9787c604adAdd missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
Luke Wren
2022-07-30 17:31:53 +0100
0567c2c9feTwo minor DM bugs: - Writes to dmcontrol.resumereq should be ignored if dmcontrol.haltreq is also set - aarsize and regno should be ignored when command.transfer is not set
Luke Wren
2022-07-30 17:22:46 +0100
c73c09a48aMore thinking about interrupt priorities
Luke Wren
2022-07-30 15:42:26 +0100
7946432d7aSpeculatively update docs with new interrupt array/priority stuff, and sleep register
Luke Wren
2022-07-28 01:18:13 +0100
add19506a5Oops, bad if block nesting in PMP
Luke Wren
2022-07-25 13:09:03 +0100
ae30d7c0d2Add instruction pseudocode (no A extension)
Luke Wren
2022-07-10 19:16:43 +0100
956b386a20Update instruction listings in docs
Luke Wren
2022-07-10 05:47:07 +0100
ee7d8e1947Bump embench for script fixes/improvements
Luke Wren
2022-07-07 18:29:37 +0100
91be98f2daMake rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
Luke Wren
2022-07-06 23:53:11 +0100
9bc72cca08Update configure line for riscv-gnu-toolchain in readme
Luke Wren
2022-07-06 22:41:32 +0100
5a39d8b7e7Track minstret and mcycle separately now that the model is cycle-accurate
Luke Wren
2022-07-06 13:50:13 +0100
5dfe5cb62bUpdate rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
Luke Wren
2022-07-06 13:49:51 +0100
b7d9defcf2Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
Luke Wren
2022-07-05 03:37:05 +0100
254350d300Clean up tie-off of hardwired PMP registers
Luke Wren
2022-07-04 14:31:42 +0100
6e80492723Typo
Luke Wren
2022-07-04 12:09:21 +0100
27793b25a1Rebase riscv-tests against upstream, and pick up new semihosting file io test
Luke Wren
2022-07-04 00:45:20 +0100
e44d2e6f9eAdd memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
Luke Wren
2022-07-03 23:34:12 +0100
cac98568e6Ignore read data from failed SBA accesses
Luke Wren
2022-07-03 20:58:01 +0100
c7a32c4d00SBA: fix alignment check using a stale address when the trigger is an sbaddress write. Fix new transfers being allowed to start when sberror or sbbusyerror are set.
Luke Wren
2022-07-03 19:02:30 +0100
ae11d04b10Add HMASTER output to processor wrappers, to indicate when the bus cycle is driven by SBA rather than the core
Luke Wren
2022-07-03 18:02:47 +0100
b1225c386cAdd missing 1port SBA change, and update example soc and bus compliance tb to reflect
Luke Wren
2022-07-03 17:57:03 +0100
9e15cd3485Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
Luke Wren
2022-07-03 15:30:33 +0100
d5cd3e0681Add SBA patch-through to 1-core wrapper. Add SBA properties to bus compliance checks. Hook up SBA in dual-core single-port debug tb.
Luke Wren
2022-07-03 15:17:44 +0100
d6bef56788Fix missing byte picking/replication in non-word-aligned SBA transfers
Luke Wren
2022-07-03 14:22:12 +0100
51bc26f8acFirst pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
Luke Wren
2022-07-03 00:25:47 +0100
36cee73d1fFix acmd FSM not selecting the correct hart signal for its state transitions, and make flush take precedence over debug injection in frontend. (Changes from aborted abstract access memory implementation, see abstract-access-memory branch)
Luke Wren
2022-07-02 22:46:20 +0100
edfe7f601eClear local monitor on non-debug trap entry/exit
Luke Wren
2022-06-26 21:55:51 +0100
a7cb214501Reduce ROM size in instruction_fetch_match: depth is more useful
Luke Wren
2022-06-26 19:59:44 +0100
c2756e79fcFix misreading of spec: hartsel hart is selected in addition to those bits set in hart array mask, when hasel is set.
Luke Wren
2022-06-26 19:58:01 +0100
fb15894731Hopefully fix case where we jump to the address immediately after a halfword-sized word-aligned predicted-taken branch, and an address-phase hold causes the jump target to go to the fetch address counter, causing a spurious BTB match on the branch.
Luke Wren
2022-06-26 15:28:06 +0100
33cec49952Fix bad predbranch tracking on a jump to a predicted-taken non-taken branch which is halfword-sized and halfword-aligned, causing CIR and PC to diverge.
Luke Wren
2022-06-26 15:22:47 +0100
5455349961Add menvcfg CSR, and comment explaining why we don't have mseccfg CSR
Luke Wren
2022-06-26 01:25:08 +0100
ad8f883406First pass at hart array mask register in DM
Luke Wren
2022-06-25 20:34:53 +0100
5193dfe477Add separate define HAZARD3_ASSERTIONS for enabling internal assertions, and enable it only on the bus compliance model checks. Trying to make the solver's life easier in instruction_fetch_match.
Luke Wren
2022-06-25 20:08:35 +0100
173f5dba9dFix jump target being unstable during a CIR-locked branch-to-self on a partial predicted branch match, due to the addr_is_regoffs decode not being tied off.
Luke Wren
2022-06-25 20:07:43 +0100
8ef9d77be8Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations. Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
Luke Wren
2022-06-25 13:11:40 +0100
31efd07042Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)
Luke Wren
2022-06-25 11:32:56 +0100
979e80be99Attempt to fix fetch mismatch caused by jumping halfway into a 32-bit instruction that precedes a taken branch.
Luke Wren
2022-06-24 19:57:45 +0100
d9389fb23eFix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
Luke Wren
2022-06-16 01:42:28 +0100
f8aad6d2f3Fix some bugs, too tired to list them, look at the diff
Luke Wren
2022-06-15 04:05:31 +0100
0766ec6f8aFirst pass at adding branch prediction
Luke Wren
2022-06-15 02:05:12 +0100
3703b1fc4cAllow use of cir_flush_behind in frontend_match formal tb
Luke Wren
2022-06-13 20:36:15 +0100
e68d8a6cd6Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
Luke Wren
2022-06-13 01:23:32 +0100
26d54d0023Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
Luke Wren
2022-06-12 20:53:53 +0100
e3da922f8bRevert previous frontend changes. Seemed promising but is a dead end for area. The original frontend design can probably be tweaked to support predictions.
Luke Wren
2022-06-12 16:25:42 +0100
940b7e4009Actually still need 7 halfwords for full throughput in the case of sequential word-sized halfword-aligned instructions
Luke Wren
2022-06-12 16:21:56 +0100
8458dff083Fix bus errors not being applied in frontend
Luke Wren
2022-06-12 05:28:21 +0100
23b4dbe7f3Redesign fetch queue: 2x32 + 3x16 -> 6x16. Should make it easier to support finer-grained flushing, and handle predicted branches cleanly.
Luke Wren
2022-06-12 02:43:15 +0100
d5a202e4a5Add standalone frontend formal tb
Luke Wren
2022-06-11 20:13:57 +0100
3b5879da66Small code cleanup in frontend. The address phase alignment state no longer needs to be tracked, since we just generate word accesses always, for simplicity.
Luke Wren
2022-06-11 14:27:59 +0100
de9b51b787Remove default zeroing of fetch address when no fetch is asserted -- this puts LUTs on a critical path and arguably causes more toggling than asserting the sequentially next address by default.
Luke Wren
2022-06-11 14:26:40 +0100
d31b1708dbMake rvpy cycle-accurate enough to get the correct Dhrystone score
Luke Wren
2022-06-09 01:34:37 +0100
11596a5bd7Remove unused/untested RISC-V timer implementation
Luke Wren
2022-06-09 00:12:26 +0100
ea2b8888a4Update copyright years
Luke Wren
2022-06-09 00:12:01 +0100
Luke Wren