Hazard3/test/sim/soc_cxxrtl
Colin 3255e9e952 Pass ECP5 fpga and jlink debug core. 2025-04-02 10:41:27 +08:00
..
.gitignore Add synth support. 2025-03-31 19:10:52 +08:00
Makefile Pass ECP5 fpga and jlink debug core. 2025-04-02 10:41:27 +08:00
compliance.cfg Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
config_default.vh Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
config_min.vh Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
gdb_init Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
gdbinit Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
multicore-openocd.cfg Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
multicore.gtkw Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
openocd-jlink.cfg Pass ECP5 fpga and jlink debug core. 2025-04-02 10:41:27 +08:00
openocd.cfg Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
soc.lpf Pass ECP5 fpga and jlink debug core. 2025-04-02 10:41:27 +08:00
softuart.c Add softuart to soc_cxxrtl test. 2025-03-30 18:36:35 +08:00
softuart.h Add softuart to soc_cxxrtl test. 2025-03-30 18:36:35 +08:00
tb.cpp Add softuart to soc_cxxrtl test. 2025-03-30 18:36:35 +08:00
tb.f Refine soc_cxxrtl and pass demo. 2025-03-27 16:02:09 +08:00
tb.v Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
tb_common.f Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
tb_multicore.f Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
tb_multicore.v Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00
waves.gtkw Add soc_cxxrtl simulation. 2025-03-26 16:28:09 +08:00