.. |
.gitignore
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Add synth support.
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2025-03-31 19:10:52 +08:00 |
Makefile
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Pass ECP5 fpga and jlink debug core.
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2025-04-02 10:41:27 +08:00 |
compliance.cfg
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
config_default.vh
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
config_min.vh
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
gdb_init
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
gdbinit
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
multicore-openocd.cfg
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
multicore.gtkw
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
openocd-jlink.cfg
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Pass ECP5 fpga and jlink debug core.
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2025-04-02 10:41:27 +08:00 |
openocd.cfg
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
soc.lpf
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Pass ECP5 fpga and jlink debug core.
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2025-04-02 10:41:27 +08:00 |
softuart.c
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Add softuart to soc_cxxrtl test.
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2025-03-30 18:36:35 +08:00 |
softuart.h
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Add softuart to soc_cxxrtl test.
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2025-03-30 18:36:35 +08:00 |
tb.cpp
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Add softuart to soc_cxxrtl test.
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2025-03-30 18:36:35 +08:00 |
tb.f
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Refine soc_cxxrtl and pass demo.
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2025-03-27 16:02:09 +08:00 |
tb.v
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
tb_common.f
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
tb_multicore.f
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
tb_multicore.v
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |
waves.gtkw
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Add soc_cxxrtl simulation.
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2025-03-26 16:28:09 +08:00 |