Colin
|
3255e9e952
|
Pass ECP5 fpga and jlink debug core.
|
2025-04-02 10:41:27 +08:00 |
|
Colin
|
b188194887
|
Add led output, refine io plan.
|
2025-04-01 18:11:04 +08:00 |
|
Colin
|
bf0e102e90
|
Add synth support.
|
2025-03-31 19:10:52 +08:00 |
|
Colin
|
2e649e2c86
|
Add softuart to soc_cxxrtl test.
|
2025-03-30 18:36:35 +08:00 |
|
Colin
|
464bd40440
|
Add softuart.
|
2025-03-30 16:23:29 +08:00 |
|
Colin
|
393499537d
|
Refine tb main.
|
2025-03-29 16:22:05 +08:00 |
|
Colin
|
aaad0d85a5
|
Enable aph port off soc, and print prints.
|
2025-03-27 23:48:10 +08:00 |
|
Colin
|
5ec810907e
|
Refine soc_cxxrtl and pass demo.
|
2025-03-27 16:02:09 +08:00 |
|
Colin
|
616da81d63
|
Add soc_cxxrtl simulation.
|
2025-03-26 16:28:09 +08:00 |