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233 Commits

Author SHA1 Message Date
Sven b5c4514b94
Update operator support planw (#367) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-04-19 11:38:07 +08:00
Antkillerfarm b916e1301a
Add Broadcast op (#365) 2022-04-18 15:45:15 +08:00
chxin66 96dedc1453
Added selu & celu & unit test (#366) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-18 14:35:29 +08:00
Antkillerfarm 954d264108
add BroadcastInDim to internal expand_broadcast op (#364) 2022-04-18 13:59:18 +08:00
chxin66 eb21143987
Support specifying pad_mode in pad (#355) 
https://github.com/VeriSilicon/TIM-VX/issues/307

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:55:47 +08:00
chxin66 479fc576ae
Suported specifying CRD_mode & DCR_mode in depthtospace (#362) 
https://github.com/VeriSilicon/TIM-VX/issues/304

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-14 19:53:32 +08:00
chxin66 0dc38eac2e
Added unit test for maxpool (#361) 
https://github.com/VeriSilicon/TIM-VX/issues/318

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 22:16:47 +08:00
lucklee 12746cb4d7
refine tim_internal.cmake for ovxlib vip (#360) 2022-04-13 22:14:32 +08:00
chxin66 93f20429ea
Fixed layout inference bug for stride_slice (#329) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:12:37 +08:00
chxin66 ba6b311409
Added hardsigmoid test case with alpha and beta (#356) 
https://github.com/VeriSilicon/TIM-VX/issues/306

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-13 10:10:30 +08:00
lucklee 1eaf326abf
update ovxlib virtual_device patch (#357) 2022-04-13 10:04:46 +08:00
chxin66 c033cfc582
Fixed compiler fail for elu (#358) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 18:42:50 +08:00
chxin66 e8ca6b8ee3
Added param step for slice & added unit test (#352) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-12 15:42:58 +08:00
Zhouheng Zheng 20e27ed550
Update prebuilt and internal for 22Q1 release(#349) 
update driver to REL/6.4.10.2
update internal to commit-id: 33cfb75b

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-04-12 15:18:45 +08:00
chxin66 d0af7ae8df
Support alpha in elu (#354) 
https://github.com/VeriSilicon/TIM-VX/issues/305

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-11 19:04:30 +08:00
Zhouheng Zheng b4091318ea
fix buf of param init in custom op (#345) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-04-06 17:21:54 +08:00
lucklee 70d2f410a8
support virtual vip devices (#331) 2022-04-06 13:05:38 +08:00
chxin66 1ca89d2ffa
Add layout inference & layout test for stack (#337) 
* Added layout inference & layout test for stack

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2022-04-06 13:01:41 +08:00
Sven 171abb0f1b
Revert "composed Dense & added unit test (#312)" (#340) 
This reverts commit f2e71a3deb.
 2022-03-31 18:37:45 +08:00
Sven 18ce7b45fb
Enable handle support for new hardware (#334) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-29 18:12:28 +08:00
chxin66 f2e71a3deb
composed Dense & added unit test (#312) 
if shape is 3D or larger, implement it as reshape + fc + reshape

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-03-25 10:49:39 +08:00
Kee 53291e99cf
Add ArgMax/ArgMin unit tests (#333) 
* Add ArgMax/ArgMin unit tests

https://github.com/VeriSilicon/TIM-VX/issues/330
 2022-03-25 09:46:50 +08:00
Sven 097f8d74cd
Refine customized op support (#327) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 23:00:52 +08:00
Sven 08500158ba
Fix build error with clang (#326) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 14:51:12 +08:00
Kee 2a8936dfed
Added unit test for batch2space and space2batch (#321) 2022-03-15 21:25:01 +08:00
Zhouheng Zheng 4d5013edf9
wrapper public ovxlib api (#320) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-15 21:24:15 +08:00
Zhouheng Zheng b02aa8b8c4
Added customize operator APIs(#315) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-09 12:10:08 +08:00
Zhouheng Zheng 161bb8a7c4
Pre-release for 22Q1 (#302) 
update internal to commit-id: d45da6fa

Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-01 17:56:03 +08:00
Sven e63059857b
Update reshape to reshape2 (#310) 
Update built-in op reshape to reshape2

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 17:04:02 +08:00
Sven c8a25d32ad
Relax tolerance for div_uint8 case (#303) 
* Relax tolerance for Div.shape_5_1_broadcast_scale_uint8
* Add tolerance for div uint8

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 10:54:56 +08:00
chxin66 3decff5398
Added unit test for STACK (#298) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-02-23 22:04:54 +08:00
chxin66 242a6bd05a
Add pad value for grouped_conv1d (#292) 
https://github.com/VeriSilicon/TIM-VX/issues/284

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-02-21 19:11:36 +08:00
Sven 6e0ac09c92
Relax tolerance for Div.shape_5_1_broadcast_scale_uint8 (#296) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-21 18:34:44 +08:00
yingshengBD f80e1b196f
Fix compile error in g++5.4 (#286) 2022-02-11 08:20:05 +08:00
Sven 7c1a00213b
[New API] Add compile_option support - relax_mode (#285) 
Added new API for tim::vx::Context::CreateGraph with a CompileOption

Only one option added in CompileOption:
    relax_mode : Run float32 mode with bfloat16

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-09 10:52:11 +08:00
Sven 86fcb0d0e0
Fix build error with gcc 6.2.0 (#282) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-27 11:42:12 +08:00
Sven 19e4e86651
Support NPU access large memory > 4G (#280) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-26 16:00:14 +08:00
chxin66 3b11a6a5b2
Added a matmul unit_test for issue 271 (#278) 
https://github.com/VeriSilicon/TIM-VX/issues/271

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-01-19 22:35:44 +08:00
chxin66 32308f62c5
Add softmax unit test (#274) 
https://github.com/VeriSilicon/TIM-VX/issues/266

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-01-19 14:54:39 +08:00
Sven a02900d135
Fix regression introduced by V1.1.37 update (#275) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-18 11:36:09 +08:00
onepick 7fa5223943
Disable float32 to float16 conversion by default(#267) 
Disable conversion since this will impact the precision. User should enable this conversion explicitly.

Signed-off-by: Jia <juku.jia@verisilicon.com>

Co-authored-by: Jia <juku.jia@verisilicon.com>
 2022-01-14 17:18:16 +08:00
liyuenan e2180a6341
Support that op's all inputs are constant (#264) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-14 12:34:38 +08:00
Antkillerfarm 36e6afa567
add alpha & beta parameters for HardSigmoid (#265) 2022-01-13 14:17:19 +08:00
Antkillerfarm 9813a5da9a
add vxc binary for internal ops (#255) 
cmake -DUSE_VXC_BINARY=1 -DVCCOMPILER_PATH=<vcCompiler path> -DGPU_CONFIG_FILE=<gpu config file> ..
 2022-01-12 11:04:49 +08:00
Zongwu.Yang 4229ad88b3
support conv3d (#238) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2022-01-11 14:13:15 +08:00
Sven ff25226adb
[Internal] support prebuilt kernel into shared library (#260) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-11 11:45:29 +08:00
Sven c1ed45150d
Added strided_slice test case with 5D-tensor (#261) 
test case can be found
    https://github.com/VeriSilicon/TIM-VX/issues/213

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-10 17:06:26 +08:00
Sven 58d2c0dedc
Fix GCC5 build error (#259) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-01-10 01:56:36 +08:00
Sven ed47c5c24c
Update internal to 1.1.37_preview (#254) 
* update internal to V1.1.37

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Update VSimulator V6.4.9 for linux x86_64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-10 01:56:00 +08:00
liyuenan 7c63ba621e
Map OneHot & unit test (#258) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-05 22:04:49 +08:00
Goose Bomb 8e4ab68213
Fix warnings relating to inheritance (#256) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance
 2022-01-04 14:35:17 +08:00
chxin66 eecbe264b6
Add a unit_test for div_uint8 (#251) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-30 13:31:30 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-29 11:08:24 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250) 
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 11:06:28 +08:00
Zongwu.Yang aed3a48248
Add layout inference and unit test for BatchNorm (#243) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-22 09:47:57 +08:00
Sven 321a53fd2a
Support single static-library for libtim-vx.a (#237) 
Fix external ovxlib build failure, and change install dir to CMAKE_INSTALL_LIBDIR

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-15 22:23:32 +08:00
chxin66 1f85d21558
mapped signal frame & unit test (#234) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-09 10:33:40 +08:00
chxin66 dc31091db5
mapped groupedconv1d & unit test (#233) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-06 19:20:13 +08:00
Zongwu.Yang bd496219c8
Add quantize, dequantize, requantize test (#232) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-02 15:40:41 +08:00
Sven 62a33ecfde
Install libtim-vx.so to lib64 if build for aarch64 (#225) 
* Install libtim-vx.so to lib64 if build for aarch64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-24 15:18:29 +08:00
Sven bc42f7987c
Fix build if lowlevel driver doesn't support DMABuffer fd (#224) 
* Fix build if lowlevel driver doesn't support DMABuffer fd

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-23 11:34:03 +08:00
chxin66 8b1ec74f07
support DMAbuffer (#214) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-21 22:46:20 +08:00
chxin66 516a914c73
Mapped Erf operation & unit tests (#211) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-10 20:07:06 +08:00
Antkillerfarm 214cbe5874
add Global Pool2d & Adaptive Pool2d (#210) 2021-11-09 20:25:02 +08:00
Sven 23ec5e9da5
Refine op status (#208) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-09 13:10:09 +08:00
Kee c9086e0afe
Update Div OP - add scale param (#203) 
Update Div OP - add scale param
 2021-11-04 10:44:52 +08:00
chxin66 e4cc133d36
Add SVDF support - only FLOAT32 supported 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-10-29 16:19:15 +08:00
Goose Bomb 914e280209
Refactor CMake build system (#184) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test
 2021-10-12 10:44:49 +08:00
Kainan Cha 404817db1f Remove unused directories from CMake 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-09-24 22:02:11 +08:00
Kainan Cha 81cc868b6c Update internal to 1.1.34 
SHA: 67f1e

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-09-24 21:36:18 +08:00
xiang.zhang 374841cbd9 Fix build error with Android NDK 
Verified with android ndk r22b

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-09-09 12:56:01 +08:00
Chen Xin 633075f689 delete Non-approximate option, recommend to use 
the approximate option

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-09-07 22:44:57 +08:00
Chen Xin 6f2e92ffa6 Add shuffle_channel support & test for tim::vx 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-09-07 22:44:57 +08:00
xiang.zhang b226777ad3 Fix average_pool unit test failure: precesion issue 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-30 19:53:01 +08:00
Chen Xin eb28f8b3ed move ArraysMatch function into src/tim/vx/test_utils.h 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-26 16:28:08 +08:00
Chen Xin 3d64cfc4ef add avgpool test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-26 16:28:08 +08:00
chxin66 5e09e98c1a
Add Gelu support for tim::vx (#153) 
* Add map for Gelu

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-17 20:37:12 +08:00
jing.tang a364c3eafb add Swish op 2021-08-16 19:30:14 +08:00
Jing.Deng 4d53e042c8 add the customer case.(only include wrong case) 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-08-13 11:57:57 +08:00
xiang.zhang e27e15925c Add unidirectional sequence lstm support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-09 13:43:33 +08:00
xiang.zhang d4a13e18a9 Minor refinement: use tensor pointer after check 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-04 11:31:26 +08:00
jing.tang f0d4118f87 Update ops doc for internal 1.1.32.1 2021-08-04 11:30:45 +08:00
Kainan Cha 6a949bb315 Add align_corners support for SpatialTransformer 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-08-03 10:52:51 +08:00
Kainan Cha 4d4bc08d6a Update internal to 1.1.32.1 
SHA: 215204

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-08-02 16:19:21 +08:00
zhao.xia 8fb3a7e6fb Remove customer test 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-07-30 11:19:32 +08:00
Your Name 70c427256d Fix groupconv2d pad parameter 2021-07-29 17:23:45 +08:00
Chen Xin a09ffe8b98 addn unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-07-22 10:41:25 +08:00
Jing.Deng 3a0bc515a1 add unit test for customer use case 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-07-22 09:55:48 +08:00
Jing.Deng f9cb2dbe45 fix the axis issue about perchannel quantized conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-07-09 14:56:39 +08:00
yuenan.li 2f8f87d1cb Add Clone API for SpatialTrasformer 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 17:34:57 +08:00
zhao.xia 8aa11f5f29 Support SpatialTransformer 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-07-06 12:56:28 +08:00
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 12:29:18 +08:00
zhao.xia 21ecf5262e Add map for Matmul 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 16:06:35 +08:00
zhao.xia 3fa2bf519a Add map for moments 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 15:58:51 +08:00
Kainan Cha 3c59694025 Update internal to 1.1.32 
SHA: 9aa0b0f

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-29 11:25:36 +08:00
Jing.Deng be066fb9bd add float32, uint8 and int8 unit_tests for transposeConv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-24 21:27:16 +08:00
Jing.Deng 1672ef99ed add uint8 and int8 unit_test for depthwise convolution. modify the api of 'conv2d' constructor 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-18 14:10:11 +08:00
xiang.zhang 574c036a69 Fix FullyConnect layer crash 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-06-16 16:05:16 +08:00
Jing.Deng c77217745f add float32 unit_test for depthwise convolution 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-13 12:03:13 +08:00
Jing.Deng e2c52d2d8a add int8 quantized unit_test for conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-10 11:38:26 +08:00