233eb439e1
Fixed viplite driver build issue ( #611 )
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Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-06-26 09:14:42 +08:00
75882d4195
Added new_axis_mask param for stridedslice ( #600 )
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Add another constructor for stridedslice when new_axis_mask is set
The layout inference need to reconstruct the axis mapping when
new_axis_mask is set(TODO)
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-25 09:24:41 +08:00
d823ef6fcb
Remove unused value in op layoutinfer ( #607 )
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Remove unused value to make sure project build successfully with higher
version compiler such as clang15
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-25 09:23:09 +08:00
26b4e53fe7
fixed reduce layoutinfer bug ( #605 )
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Type: Bug fixed
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-06-19 21:56:08 +08:00
fbfbdd7c83
Added axis support for layernorm ( #602 )
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Layernormolization can handle non zero axis now
Added case to verify layernorm with axis 2
Modify layernorm opjson
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-06-15 21:45:46 +08:00
a64a0f7379
Added a case for resize_bilinear layoutinfer ( #595 )
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Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-06-02 07:52:06 +08:00
ea8adc456a
fixed instance norm bug & add its layoutinfer ( #593 )
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Type: Bug fix
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-31 12:55:42 +08:00
4f92e58155
optimization for tiny_yolov4 ( #591 )
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Type: code improvment
Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-23 14:28:47 +08:00
51faf286c2
Fixed LayerNormalization eps bug ( #589 )
2023-05-22 14:13:44 +08:00
99606fd891
Add a case for local response norm ( #590 )
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Signed-off-by: Chen <jack.chen@verisilicon.com>
Co-authored-by: Chen <jack.chen@verisilicon.com>
2023-05-20 16:57:21 +08:00
ddcb00c11b
Fixed bug for pad test ( #588 )
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Type: Bug fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-05-20 16:56:00 +08:00
3c372dd646
Refine UnidirectionalGRU and GRUCell ( #587 )
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Refine unidirectional_gru and gru_cell code to avoid including ovxlib files
in header of some op
Introduce TranslateToVsibool function to support above code refinement
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-05-15 16:44:51 +08:00
b81f7979fa
Reload "==" operator for quantizations of two tensor ( #583 )
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Reload operator "==" to check two quantization same or not
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-05-10 17:58:30 +09:00
308a967bcf
Support build openssl from local repo ( #582 )
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Type: Code Improvement
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-05-05 23:38:39 +08:00
1543efe098
Add some tensor dtype convert APIs ( #576 )
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For pre/post process.
Type: Code Refine
Co-authored-by: wangqian <wangqian@CNCDD9444.verisilicon.com>
2023-04-27 09:04:39 +08:00
c688ca6e81
Fixed ovxlib build error on android ( #578 )
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-04-26 16:59:52 +08:00
3c5ee7a46e
Refine prelu layout inference ( #577 )
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In the past we reverse all inputs to default order pv and caused
unnecessary transpose operation.
In this commit only const slope will be handled and do transpose if necessary.
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-04-25 11:25:55 +08:00
3a3c9fa5fa
Update readme in ops ( #575 )
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Added missing ops which have already supported; Changed status of some
ops.
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-04-20 13:23:56 +08:00
f1fd2246ae
Support tensor cache while create tensor ( #574 )
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Support tensor cache while create tensor
Tensor can be shared between different operations, if tensor have
identical data and quantization parameter, they should share same
low-level tensor object to save memory.
In tim-vx, introduce a tensor cache which key is md5sum and value is
low-level tensor object. If up-coming tensor have same md5sum, the
cached tensor object reused for tensor creation.
Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-04-19 21:31:25 +08:00
6e38e64a1a
Update internal & prebuilt-sdk for 23Q1 release ( #573 )
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Update internal to 0e9393dbb4f653b9dfceaeaaa920d4deb8b27077
Update prebuilt-sdk to 6.4.14 release
Update cmakefiles to support above updates
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-04-18 22:19:16 +08:00
a32f255d7f
Modified error to warning when check consumed tensor ( #572 )
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If graph has free INPUT or OUTPUT, modified error to
warning when check in graph compile
Type: Code refine
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-04-10 13:28:51 +08:00
27890719b6
Support remote platform by gRPC ( #561 )
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* Support remote platform by gRPC
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2023-03-28 09:51:23 +08:00
c2755b90ea
Fixed l2normalization layout infer bug ( #570 )
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And added a case
Type: Bug fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-03-27 15:00:25 +08:00
e49f67b840
Remove tensor GetDataRef api ( #569 )
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Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
2023-03-23 21:35:30 +08:00
6424ef104e
Fixed the IOtensor order difference between src_graph and infer_graph
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* Fixed the IOtensor order difference between src_graph and infer_graph
Graph Input/Output tensor sequence may changed after graph
transformation(layout infer), it is difficult to get the IO mapping
between original graph and final graph.
Clients such as the Android Support Library create tensors using the
original input/output order, which may not be the same as the input
order of src_graph, the data can not be setup correctly.
Solution:
Decide the order of inputs/outputs while creating tensor not at binding to
operation. The order of binding could be change in each transform.
Type:Code improvement
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
* Fixed maxpoolgrad maxpoolwithargmax2 cases
Some tensors created with wrong attr
Type: Bug fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
---------
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2023-03-21 09:21:15 +08:00
958b26e499
Fix mirror pad param mismatch
2023-03-21 09:20:00 +08:00
f0a0f1728a
Added case for hardswish
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-03-06 09:37:13 +08:00
e71d537042
Fixed deconv2d layout infer bug
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Type: Bug fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-02-20 13:06:24 +08:00
1c6041c394
Introduce CMAKE option TIM_VX_DBG_DISABLE_TENSOR_HNDL=OFF
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Enable/Disable tensorFromHandle usage
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2023-02-09 14:31:32 +08:00
ea4ba66b94
Refine Depth2Space op
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Change default mode from CRD_mode to DCR_mode
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-02-09 13:19:57 +08:00
5e7f5cecea
Fixed grouped_conv2d layout infer & Added cases
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added cases for conv2d/grouped_conv2d
Type: Bug fixed
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-01-20 15:28:21 +08:00
d778dfb82d
update copyright information
2023-01-20 12:49:48 +08:00
9ab00a57a6
Fixed Invalid read of size 8 reported by Valgrind
2023-01-11 21:31:31 +08:00
58d36ab943
Added reduce_all layoutinfer & reduce cases
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Type: New feature
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2023-01-09 09:30:44 +08:00
789d4458ff
Added 4d quantized LUT unittest for embedding_lookup
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Type: New Feature | Bug Fix | Code Improvement | Documentation
Issue: bugzilla id | jira id #No more newline after this
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-01-09 09:28:45 +08:00
06d4747b31
Fixed wrong type of hashtable_lookup unit test
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Modified datatype of copied output so that actual float16 output can be
checked correctly
Type: Bug Fix
Issue: Bug 34696
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2023-01-03 15:10:25 +08:00
cc34b5f0ea
mapped pool1d
2022-12-30 10:52:28 +08:00
aa0b474c19
Added a case for fc
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-30 10:34:21 +08:00
c1f8a959af
Fixed bug for pad_v2
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-30 10:19:03 +08:00
0e211c8efd
Fixed (groupd)conv2d layout infer bug
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And added a weight_as_input case to test
Type: Bug Fix
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-16 15:20:56 +08:00
ac4517b5c1
Added EmbeddingLookup 4d support internal
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Added EmbeddingLookup internal support for 4d lut input
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-16 15:09:19 +08:00
06b88e7940
Fixed nn_params in groupconv2d
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Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-16 15:08:14 +08:00
c6919248e1
fixed groupconv2d params in internal
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Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-16 15:04:54 +08:00
7582b57edc
Added pad_v2 & pad_v2 layout infer
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And added 4 rank case
Type: Added new op
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-12-16 15:03:58 +08:00
8d8f4b6e68
Added EmbeddingLookup & deprecate LshProjection
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Added EmbeddingLookup and unit test
Changed LshProjection op status to Deprecated
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-05 09:59:56 +08:00
13da73bbe3
Fix maxpoolgrad, hide unused pool value output
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Type: Bug Fix
2022-12-01 15:49:38 +08:00
b7478f7872
Added invalidate handle marco
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Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-01 15:37:33 +08:00
f7b49ae4e2
Modified README.md about rnn&lstm
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Changed status of UnidirecitonalRnn&BidirectionalRnn
Changed status and internal op of BidirectionalLstm
Type: Documentation
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-01 10:56:48 +08:00
dd7cd2504c
Added HashtableLookup Op
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Added HashtableLookup Op and unit test
Type: New Feature
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-12-01 10:55:21 +08:00
c231c54a66
Fixed BidirectionalSequenceRnn bugs
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Added layout inference for BidirectionalRnn
Fixed wrong datatype and wrong output order of internal about backward rnn
Corrected golden in BidirectionalRnn&BidirectionalRnnExt unit test
Modified copyright and log message
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-28 09:45:50 +08:00
05a1c561af
Added layout_inference for UnidirectionalRnn
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Added layout_inference so that can support tflite cases
Modified copyright of code
Modified case name and value name in UnidirectionalRnn unittest
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-23 20:58:00 +08:00
8cd5bd93ce
Add BUILD_WITH_BAZEL option, marco of VSI_FEAT_OP_XXX should behind headers now.
2022-11-22 21:39:02 +08:00
d723ffaf51
fix typo for graph_test.cc
2022-11-22 21:37:40 +08:00
545d677160
diabled a failed case
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-22 21:36:41 +08:00
9fe7b955e5
Fixed average pool layout infer
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-16 13:34:31 +08:00
883334e1bb
add rnn
2022-11-16 13:33:39 +08:00
11fd278d7a
Fixed BidirectionalSequenceLSTM bug
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Fixed input error of the backward direction
Fixed golden error of unit test
Type: Bug Fix
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-11-16 13:31:23 +08:00
4db479ece4
Set RNN internal dtype
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Init RNN internal dtype to avoid the
internal FC OP to go to the CPU path
Type:Code Improvement
Signed-off-by: Kee <xuke537@hotmail.com>
2022-11-14 09:39:27 +08:00
6816a0188a
Added minimum unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-11 18:03:46 +08:00
8867c8de35
Fixed roi_align golden mismatch error
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-11-11 18:02:36 +08:00
ed162d0176
Update internal for 22Q3 release
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update internal to commit-id: e2b0fde631fce349e0e3ad42b2a4d40ce7634a97
Type: Code Improvement
Signed-off-by: Feiyue Chen <Feiyue.Chen@verisilicon.com>
2022-10-24 15:34:53 +08:00
3fed6d6757
fixed bug when broadcast dimensions is negative
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-10-08 21:42:02 +08:00
a038df2a84
added transpose_test from https://github.com/VeriSilicon/TIM-VX/issues/429
2022-10-08 14:47:07 +08:00
20db77ee61
Added two cases in strided_slice
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-29 20:24:09 +08:00
535c9da867
Fixed bug when input's index is not 0
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-28 16:48:16 +08:00
4c6299e7fd
Added two reduce layout infer unittest
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-28 09:37:38 +08:00
72f2c5b69e
Supported composed layout infer & added unit test
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Fixed fc layout infer in rnncell layout infer
2022-09-26 14:29:46 +08:00
1802e558ad
modified cumsum header && resolve conflict in README.md
2022-09-26 14:27:48 +08:00
264e491d2a
added cumsum op & added handle api after BindInput
2022-09-26 14:27:48 +08:00
9cb37b920f
added MaxPool3d op
2022-09-26 13:32:56 +08:00
8b8d09aea3
added Rcp op & modified test_utils
2022-09-22 12:15:02 +08:00
1b07b022e2
added sign & softsign
2022-09-20 22:49:45 +08:00
f4d5e170de
added & modified copyright of some files
2022-09-20 22:47:33 +08:00
84b464ee8b
Update README.md
2022-09-20 22:47:33 +08:00
6099022f00
added Mod op & Mod unit test
2022-09-20 22:47:33 +08:00
9b13b6f677
Replace name direct_map_op with builtin_op
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-19 10:21:19 +08:00
113c3722cb
supported int16 dfp quantization & added conv2d unit test
2022-09-15 22:15:22 +08:00
95401036ab
fixed some errs on gcc12
2022-09-15 21:26:43 +08:00
6d9ed7b25b
Disabled a conv3d case
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because of some branches are not fully supported
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-15 10:46:05 +08:00
0bb547b8e4
disabled two Div cases
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int32 type not supported in branch 234062
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-06 23:58:03 +08:00
e62b62015d
Added conv3d unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-06 11:45:24 +08:00
e9771746ba
Fix error in feature compatiable guard
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Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-09-05 15:05:50 +08:00
f348c8e36c
disabled two not supported cases
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-09-05 14:52:59 +08:00
9de8df404c
Feat: disable maxpoolwithargmax2 feature if no low-level feature avaiable ( #471 )
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Convert operation list as compiler flags in cmake, when add new
operation in tim-vx, always check if the feature define is available or
not - so that tim-vx can compile with legacy ovxlib library.
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
2022-09-01 18:56:49 +08:00
f6121140b0
Mapped unidirectional gru & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-31 09:27:05 +08:00
58395cf7a7
Modified bidirectional_sequence_lstm golden accuracy
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-31 09:26:07 +08:00
80fed36ea3
Modified Div_int unit test golden
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Signed-off-by: root <root@DESKTOP-K365DSV.localdomain>
2022-08-30 10:28:09 +08:00
1c640c6f10
Mapped bidirectional lstm & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-22 10:42:05 +08:00
96d186c8d2
Set graph attributes when compile graph to binary
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Keep the same graph attributes as compile graph
Signed-off-by: Kee <xuke537@hotmail.com>
2022-08-15 06:34:08 +08:00
944fdfad8f
Mapped GRUCell & unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-11 20:34:19 +08:00
03b5ec2d17
Added div int32 unit test
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-11 14:37:34 +08:00
a5ba633fe4
add readme for ovxlib_bin_build.sh
2022-08-08 16:52:45 +08:00
9a28ff5758
Fix the build error for clang when export TIM_VX_ENABLE_PLATFORM=ON
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Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
2022-08-08 16:50:25 +08:00
3663a99e0f
Fixed param compute bug for lrn
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-08-04 21:35:59 +08:00
6d47ee3ac1
Expose hw feature : isClOnly()
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Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
2022-08-03 09:06:32 +08:00
27b4298b29
Fixed quantize param in reduce_sum
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
2022-07-29 11:12:09 +08:00
9ebddb5452
add op: maxpoolwithargmax2 and maxpoolgrad
2022-07-29 11:11:33 +08:00
84d76e5251
fixed: maxpoolwithargmax's output1 have wrong shape, internal id: I7d5aeab58038bacb73373a4ff4f48a12bb6441db
2022-07-29 11:11:33 +08:00
32241dc4ad
Rename RoiAlign & RoiPool ( #446 )
2022-07-29 11:10:25 +08:00
96c9d5df01
Added cases for reduce sum ( #441 )
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Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
2022-07-27 12:53:56 +08:00
chxin66
Chen Feiyue
shijie001
SCUWQ
liyuenan
Zhouheng Zheng
zhouheng.zheng
Chen Xin
ZhangXiang
Feiyue Chen
Tang
Huanyu.Cai
meseraph
Qin.Chen
Kee
root
yuenan.li
Antkillerfarm