cb5a7a141d
Update dmi_jtag_to_core_sync.v
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Follow syntax used in internal repository.
2020-02-24 15:00:46 -06:00
2a1d9be0c2
Update dmi_jtag_to_core_sync.v
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Fixed incorrect syntax
2020-02-24 14:52:54 -06:00
b65d4dd8f1
Version 1.5
2020-02-19 18:25:04 -08:00
790c48cd0b
Version 1.5
2020-02-19 18:24:28 -08:00
aa2bc2269d
Fixed FPGA build error
2019-12-06 09:50:38 -08:00
3820e84e20
Move declarations to top of Verilog file to fix fpga compile issues.
2019-10-15 13:14:36 -07:00
811e9c3d24
Change clock header instance name in beh_lib.sv
2019-09-04 14:39:10 -07:00
b35d7e9e1b
Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
2019-09-04 13:29:39 -07:00
7ff8d7fb5a
Untabified files.
2019-08-13 12:48:48 -07:00
6a528a9a8b
Ignore ebreak/ecall w.r.t MINSTRET
2019-08-09 19:18:41 -07:00
1cf98e765d
fix synthesis syntax in rvdffe in beh_lib.sv
2019-08-08 07:51:56 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
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not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
e40f01e15d
Moved flist.questa to testbench directory.
2019-07-12 11:25:07 -07:00
0f3f246df5
Remove spurious carriage return characters.
2019-07-12 06:22:01 -07:00
5990932214
Removed apostrophe from comment.
2019-07-12 06:04:31 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
jrahmeh
Joseph Rahmeh
Arup De