a44ef01adf
Changed version to 1.5.
2020-02-18 13:41:42 -08:00
9228e01812
Added release notes for version 1.5.
2020-02-18 13:40:11 -08:00
e57b032cd7
makefile updated for ALDECs riviera
2019-12-12 08:46:21 +01:00
6ca86d86a9
makefile updated for ALDECs riviera
2019-12-12 08:45:34 +01:00
1651bdf99a
Merge pull request #29 from arupde171/master
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Fixed FPGA build error
2019-12-06 17:50:19 -05:00
aa2bc2269d
Fixed FPGA build error
2019-12-06 09:50:38 -08:00
c89f6b7511
Update README.md
2019-11-20 11:02:15 -08:00
9840fabd5c
Added SweRV CoreMark document
2019-11-20 10:39:09 -08:00
fb5ebdea26
Add Verilator to the PATH
2019-10-16 17:47:14 -04:00
51b8e54ff6
Add Travis CI
2019-10-16 16:55:27 -04:00
3820e84e20
Move declarations to top of Verilog file to fix fpga compile issues.
2019-10-15 13:14:36 -07:00
5fce5b0a26
Update README.md
2019-09-08 11:15:25 -04:00
cf4d56c78c
Added basic commit register update trace in exec.log
2019-09-08 11:13:17 -04:00
761e69df4e
Update release-notes.md
2019-09-04 17:44:15 -04:00
811e9c3d24
Change clock header instance name in beh_lib.sv
2019-09-04 14:39:10 -07:00
35bc589b09
Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV
2019-09-04 13:32:48 -07:00
b35d7e9e1b
Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
2019-09-04 13:29:39 -07:00
fc331027c2
Conditioned declaration of finished per issue #13
2019-09-03 21:35:43 -04:00
2108e722c8
Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV
2019-08-13 15:48:48 -07:00
68f4383d96
Update RISC-V SweRV EH1 PRM.pdf
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Rev. 1.2
2019-08-13 15:48:28 -07:00
4e161e6c3b
Minor cleanup in config script.
2019-08-13 15:47:53 -07:00
189ce25027
Updated release notes
2019-08-13 16:42:26 -05:00
8242950a58
Fixed branch numbers
2019-08-13 15:30:00 -05:00
c5a699aa40
Fixed release notes
2019-08-13 15:08:45 -05:00
d9bb036633
Updated hello world message. Updated last compilation time.
2019-08-13 12:57:04 -07:00
7ff8d7fb5a
Untabified files.
2019-08-13 12:48:48 -07:00
85a510db19
Updated release notes.
2019-08-13 12:43:09 -07:00
ac92841999
Adjust CSR MFDC reset value for the AXI bus.
2019-08-13 12:38:50 -07:00
e20f012de7
Removed refernce to version 1.1.
2019-08-10 13:42:48 -07:00
40db638de6
Mention 1.1.1 release.
2019-08-10 13:23:53 -07:00
e7f57a0d5d
Added 1.1.1 release notes.
2019-08-10 13:23:08 -07:00
6a528a9a8b
Ignore ebreak/ecall w.r.t MINSTRET
2019-08-09 19:18:41 -07:00
1cf98e765d
fix synthesis syntax in rvdffe in beh_lib.sv
2019-08-08 07:51:56 -07:00
0dacc978da
Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
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not start an SB write access when sbreadonaddr/dbreadondata is set.
Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
bc367eaf3a
Update README.md
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Added description of "espresso".
2019-07-20 08:28:44 -05:00
8c413fd1e2
Removed invalid include statement.
2019-07-12 11:26:03 -07:00
e40f01e15d
Moved flist.questa to testbench directory.
2019-07-12 11:25:07 -07:00
0f3f246df5
Remove spurious carriage return characters.
2019-07-12 06:22:01 -07:00
5990932214
Removed apostrophe from comment.
2019-07-12 06:04:31 -07:00
412c128fb0
Removed duplicate declaration of finished for Verilator.
2019-06-20 09:50:50 -07:00
8f92cd5033
Added .gitignore file.
2019-06-20 08:48:50 -07:00
48dc8668cb
Update README.md
2019-06-09 19:50:35 -05:00
166274de5e
Update README.md
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Added reference to version 1.0.
2019-06-06 11:32:35 -05:00
56db557851
Update release-notes.md
2019-06-04 11:31:56 -05:00
d33df11a5b
Added release notes.
2019-06-04 09:29:22 -07:00
9c6d925379
Create RISC-V SweRV EH1 PRM.pdf
2019-06-04 10:54:09 -05:00
de6978de5d
SweRV 1.1
2019-06-04 07:58:40 -07:00
c0f7e509cc
SweRV 1.1
2019-06-04 07:57:48 -07:00
6ccfce0957
Update README.md
2019-06-01 23:45:59 -07:00
1abeb9a380
Update README.md
2019-06-01 23:44:30 -07:00
Joseph Rahmeh
danielm
aprnath
Arup De
Arup De
Todd Strader
Ajay Nath
tmw-wdc
jrahmeh
Zvonimir Bandic