Commit Graph

180 Commits

Author SHA1 Message Date
colin 5b6bdcc8b0 Update .gitignore. 2022-03-22 23:24:30 +00:00
colin 388db4a82e Delete quasar in Cores-SweRV. 2022-03-22 23:24:01 +00:00
colin 386e1f1a54 Add Miner420T submodule 2022-03-22 23:14:02 +00:00
colin be80eb1063 Update Quasar. 2022-03-20 09:06:23 +00:00
colin 49c8aab2fd Update Readme. 2022-03-20 09:06:02 +00:00
colin 03549f1f93 Update Quasar 2022-03-18 10:06:26 +00:00
colin b2c15ca508 Update xilinx Readme. 2022-03-11 05:08:19 +00:00
colin b9d70b7a1c Update Quasar 2022-03-10 13:15:49 +00:00
colin d806515276 Add submodule of quasar. 2022-03-10 08:58:15 +00:00
colin 2be1901f7b update EL2 2022-03-09 14:46:24 +00:00
colin e513374a7e Add submodule of sweRV EL2. 2022-03-09 11:17:07 +00:00
colin beab126fc5 add quasar fpga. 2022-03-09 11:16:13 +00:00
colin 33885bbccb Add Bit-Vector install in readme 2022-03-07 04:08:12 +00:00
colin 27fade0b6d Add EL2 cores implement by Chisel in quaser. 2022-03-06 04:22:17 +00:00
colin 0a00e20cfe Update riscv gcc version and usage. 2022-03-06 04:21:41 +00:00
colin 3da81c5916 Add install commond in riscv gnu tools. 2022-03-01 13:22:23 +00:00
colin e26d5260de start to add ecp5 support,current donet support jlink
Use FT2232H base jtag,and VexRiscv's openocd to support dbg.
2022-02-28 03:34:59 +00:00
colin 2c4658ddb9 Refine murax sim config file 2022-02-28 03:33:41 +00:00
colin 28d08fc3ad Refine Readme of install openocd. 2022-02-28 03:33:08 +00:00
colin e0f77ceead Add configuration to flash by ecpdap. 2022-02-27 15:39:45 +00:00
colin 94c99367ba remove gen file in fpga 2022-02-27 04:49:27 +00:00
colin 1d1237c223 Add VexRiscv fpga generation to ecp5. 2022-02-26 15:14:43 +00:00
colin 25a557365b Enable VexRiscv murax jtag simulator by verilator. 2022-02-26 14:34:25 +00:00
colin e3968e6fa7 Refine opene906 gdb sample. 2022-02-25 12:24:03 +00:00
colin 65545d5e03 Add VexRiscv. 2022-02-25 11:56:36 +00:00
colin ccc993e003 Refine gdb sample code 2022-02-24 06:04:58 +00:00
colin 3258c057e3 Enable demo openocd and gdb. 2022-02-24 03:18:07 +00:00
colin 1d7ba86749 Add dome on opene906 2022-02-22 06:44:45 +00:00
colin 0d940ba004 Add opene906 2022-02-21 10:41:54 +00:00
colin 51730ed20d Add xilinx readme. 2022-02-21 07:53:02 +00:00
colin 3972a891ca Add fpga demo in Cores. 2022-02-21 07:52:52 +00:00
colin 3edc87e0ea Switch mem bus from ahb to axi. 2022-02-17 11:35:01 +00:00
colin cffec82632 Add clean before fpga ram make all 2022-02-17 06:21:42 +00:00
colin 8e190efed0 Split from soc.mk to soc_sim.mk and soc_top.mk 2022-02-15 08:31:00 +00:00
colin 1f222dd1e3 Split soc and verilator to two part system verilog. 2022-02-14 12:32:21 +00:00
colin a6038fde4a Set DCCM and ICCM size to 32KB 2022-02-11 12:17:21 +00:00
colin 547f0dbdc3 remove axi4 in demo soc use ahb as default 2022-02-10 12:17:10 +00:00
colin 18c8352c09 Add ram test and verilator in fpga DEMO. 2022-02-09 12:47:35 +00:00
colin 3c3cfccfd5 add ram test. 2022-02-08 03:00:40 +00:00
colin a7ef641f0d Refine io level 2022-02-07 13:34:50 +00:00
colin 3405c88c9e Correct blink and use sample blink code 2022-02-07 13:23:34 +00:00
colin 3370d01917 Add verilator install method in readme. 2022-02-07 08:13:16 +00:00
colin 3ba8533996 Add fpga 2022-02-02 03:43:53 +00:00
colin a15c797e93 add jtag to ESP32 2022-02-02 03:40:41 +00:00
colin 853d12f17c Init to abstract accelerator project 2022-02-02 03:34:37 +00:00
colin f299211d91 Refine readme for rocket tool build 2022-02-01 15:50:30 +00:00
Colin d8c2a6861b refine Readme for demo 2022-01-27 16:42:31 +08:00
Colin 3ed8011eaa add jtag demo for GDB which openocd 2022-01-22 08:08:47 +00:00
Colin 5f80832b1a add jtag demo and refine Makefile 2022-01-20 03:44:59 +00:00
Colin a8fc3642ad Add dpi of jtag 2022-01-19 12:45:38 +00:00