Commit Graph

23 Commits

Author SHA1 Message Date
Olof Kindgren bcf505751e Remove unused scan_mode input from dmi_wrapper
This causes the dmi wrapper from SweRV EH1 and SweRV EL2 to have
the same interface which makes it easier to use the two CPU cores
interchangeably in a design.
2021-01-18 10:15:08 +01:00
Joseph Rahmeh 5e613582c2 New branch: branch1.8 2020-09-18 13:34:02 -07:00
Joseph Rahmeh 8065eef677 Branch for version 1.7 2020-06-25 19:59:36 -07:00
Joseph Rahmeh 0555dd8763 Reverted change related to enum assign as it broke some Verilog tools. 2020-05-27 14:50:39 -07:00
jrahmeh 27507b79a1
Merge pull request #49 from dawidzim/enum_from_diff_type
fix for assignment to enum variable from expression of different type
2020-05-27 08:38:13 -05:00
Joseph Rahmeh 6b1e5ded3a Version 1.6 2020-05-15 11:28:59 -07:00
Dawid Zimonczyk 241ad18e25 fix for assignment to enum variable from expression of different type 2020-04-02 15:48:17 +02:00
jrahmeh cb5a7a141d
Update dmi_jtag_to_core_sync.v
Follow syntax used in internal repository.
2020-02-24 15:00:46 -06:00
jrahmeh 2a1d9be0c2
Update dmi_jtag_to_core_sync.v
Fixed incorrect syntax
2020-02-24 14:52:54 -06:00
Joseph Rahmeh b65d4dd8f1 Version 1.5 2020-02-19 18:25:04 -08:00
Joseph Rahmeh 790c48cd0b Version 1.5 2020-02-19 18:24:28 -08:00
Arup De aa2bc2269d Fixed FPGA build error 2019-12-06 09:50:38 -08:00
Joseph Rahmeh 3820e84e20 Move declarations to top of Verilog file to fix fpga compile issues. 2019-10-15 13:14:36 -07:00
Joseph Rahmeh 811e9c3d24 Change clock header instance name in beh_lib.sv 2019-09-04 14:39:10 -07:00
Joseph Rahmeh b35d7e9e1b Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module. 2019-09-04 13:29:39 -07:00
Joseph Rahmeh 7ff8d7fb5a Untabified files. 2019-08-13 12:48:48 -07:00
Joseph Rahmeh 6a528a9a8b Ignore ebreak/ecall w.r.t MINSTRET 2019-08-09 19:18:41 -07:00
Joseph Rahmeh 1cf98e765d fix synthesis syntax in rvdffe in beh_lib.sv 2019-08-08 07:51:56 -07:00
Joseph Rahmeh 0dacc978da Merged bug fix corresponding to Jira RISCV-1454: Write to SBDATA0 does
not start an SB write access when sbreadonaddr/dbreadondata is set.

Add fpga_optimize option to swerv.config; eliminates over 90% of
clock-gating to support faster FPGA simulation.
2019-08-07 17:04:48 -07:00
Joseph Rahmeh e40f01e15d Moved flist.questa to testbench directory. 2019-07-12 11:25:07 -07:00
Joseph Rahmeh 0f3f246df5 Remove spurious carriage return characters. 2019-07-12 06:22:01 -07:00
Joseph Rahmeh 5990932214 Removed apostrophe from comment. 2019-07-12 06:04:31 -07:00
Joseph Rahmeh c0f7e509cc SweRV 1.1 2019-06-04 07:57:48 -07:00