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  • 3be1146718 refine define file build Colin 2022-01-17 11:40:11 +0000
  • 1d8069026b remove no use file in demo Colin 2022-01-17 11:10:22 +0000
  • 2b298f0fff rename test to demo Colin 2022-01-17 06:43:14 +0000
  • 0eb74fdc10 refine test use function Colin 2022-01-05 03:47:27 +0000
  • 6567357739 add llvm build flow from .c file Colin 2022-01-04 12:39:14 +0000
  • be63e84a1d Add build from llvm Colin 2021-12-17 13:29:59 +0000
  • 911f65874f add test of verilator in one folder Colin 2021-12-16 12:07:50 +0000
  • 87c23b9952
         Merge pull request #101 from antmicro/fix-vivado-tcl Ajay Nath 2021-10-08 17:45:03 -0400
  • f57cce19ff Remove not existing file from vivado.tcl Kamil Rakoczy 2021-08-27 15:27:02 +0200
  • 81bff1c0d7 reverting to 0242c9e for swerv_config_gen.py Ajay Nath 2021-03-12 08:02:57 -0500
  • d4e7b25f71
         Merge pull request #93 from antmicro/variable-order-fix Ajay Nath 2021-02-19 15:03:43 -0500
  • 74a6bdb50d Do not use variables before declaration Tomasz Gorochowik 2021-02-17 10:58:22 +0100
  • f3da044f15
         Delete testbench/tests/cmark_dccm directory Ajay Nath 2021-02-16 08:56:23 -0500
  • 5e23462bd0
         Update README.md Thomas Wicki 2021-02-03 13:26:41 -0800
  • 695883a674 Removed dead code. Joseph Rahmeh 2021-02-03 11:08:48 -0800
  • 0c92ea167b Version 1.9 Joseph Rahmeh 2021-02-03 07:07:10 -0800
  • ec254f5491 Version 1.9. Joseph Rahmeh 2021-01-27 09:36:43 -0800
  • bcb5b33726
         Merge pull request #82 from chipsalliance/quartus_core_fix Ajay Nath 2021-01-21 17:59:41 -0500
  • bb9f9ef37b
         Merge pull request #89 from olofk/scan_mode Ajay Nath 2021-01-21 17:58:36 -0500
  • bcf505751e Remove unused scan_mode input from dmi_wrapper Olof Kindgren 2021-01-15 17:14:47 +0100
  • 3918a8d345
         Only load Vivado TCL files when using Vivado Olof Kindgren 2020-11-24 09:31:52 +0100
  • 7332edc0ad
         Merge pull request #76 from olofk/snapshot_dir2 Ajay Nath 2020-09-24 10:26:32 -0400
  • 0242c9e6d2 Explicitly use python3 Olof Kindgren 2020-09-24 15:24:30 +0200
  • 801d0f66f6 Set snapshot dir to a known location in FuseSoC SweRV config generator Olof Kindgren 2020-09-24 14:32:08 +0200
  • 1e8c6e3813
         Merge pull request #75 from olofk/snapshot_dir Ajay Nath 2020-09-22 13:41:35 -0400
  • 2627ccc82b Adapt FuseSoC SweRV config generator wrt new snapshot dir Olof Kindgren 2020-09-22 16:27:04 +0200
  • f32b634c16 Updated per issue #70 Ajay Nath 2020-09-22 09:58:03 -0400
  • 3c50837a75
         Update release-notes.md Thomas Wicki 2020-09-18 18:00:45 -0700
  • e63dfe17d8 Updated version in swerv.core Joseph Rahmeh 2020-09-18 14:42:34 -0700
  • d6024bcc6b Updated branch number in README file. Joseph Rahmeh 2020-09-18 14:08:43 -0700
  • d395a96492 Updated branch number in README file. Joseph Rahmeh 2020-09-18 14:03:24 -0700
  • 8caf5f69b0 Added testbench/hex directory. Joseph Rahmeh 2020-09-18 13:47:53 -0700
  • 95e9589446 Updated PRM. Joseph Rahmeh 2020-09-18 13:47:21 -0700
  • 5e613582c2 New branch: branch1.8 Joseph Rahmeh 2020-09-18 13:34:02 -0700
  • 499378d0c6
         Merge pull request #68 from olofk/fusesoc_v1_7 jrahmeh 2020-08-19 12:03:59 -0500
  • 9e0aeed92e Update SweRV version in core description file to 1.7 Olof Kindgren 2020-08-19 18:25:32 +0200
  • 48f01f101e
         Update README.md Thomas Wicki 2020-06-26 15:02:13 -0700
  • 5f905a0912 Upped version. Joseph Rahmeh 2020-06-26 10:24:06 -0700
  • ae1b1bccad Updated PRM. Joseph Rahmeh 2020-06-26 09:55:56 -0700
  • 8065eef677 Branch for version 1.7 Joseph Rahmeh 2020-06-25 19:59:36 -0700
  • 0555dd8763 Reverted change related to enum assign as it broke some Verilog tools. Joseph Rahmeh 2020-05-27 14:50:39 -0700
  • 5a004dd2b6
         Merge pull request #55 from dawidzim/riviera_fusesoc jrahmeh 2020-05-27 10:55:32 -0500
  • 27507b79a1
         Merge pull request #49 from dawidzim/enum_from_diff_type jrahmeh 2020-05-27 08:38:13 -0500
  • 23c6ce84dc update swerv.core for Riviera-PRO Dawid Zimonczyk 2020-05-26 15:17:59 +0200
  • ee7473ee90
         SweRV core roadmap white paper Zvonimir Bandic 2020-05-20 18:23:44 -0700
  • a4cc4368ad Update RISC-V_SweRV_EH1_PRM.pdf tmw-wdc 2020-05-15 15:22:32 -0700
  • 977175e264
         Add 'V' to to title Thomas Wicki 2020-05-15 14:21:49 -0700
  • 0b2ec70608
         Update version from 1.5 to 1.6 Thomas Wicki 2020-05-15 14:20:29 -0700
  • d2a6fac636 Version 1.6 Joseph Rahmeh 2020-05-15 13:04:43 -0700
  • 83d5753bad Version 1.6 Joseph Rahmeh 2020-05-15 11:40:52 -0700
  • 6b1e5ded3a Version 1.6 Joseph Rahmeh 2020-05-15 11:28:59 -0700
  • 21fe37b5e2
         Merge pull request #20 from toddstrader/master aprnath 2020-04-13 16:03:04 -0400
  • cc6285eb3b remove unnecessary switch from vlog Dawid Zimonczyk 2020-04-02 16:38:56 +0200
  • 241ad18e25 fix for assignment to enum variable from expression of different type Dawid Zimonczyk 2020-04-02 15:48:17 +0200
  • 26c3bcb78f
         Merge pull request #42 from danielmlynek/readme_upd_for_aldec1 aprnath 2020-03-04 11:13:19 -0500
  • f2e40ff2c8
         Update README.md Thomas Wicki 2020-02-28 14:21:35 -0800
  • cbb7080411 Update RISC-V_SweRV_EH1_PRM.pdf tmw-wdc 2020-02-28 14:19:14 -0800
  • 040d2807c9 Fix Riviera -l switch Daniel Mlynek 2020-02-27 09:59:42 +0100
  • e1aec7d193 Riviera simulator added to Readme Daniel Mlynek 2020-02-27 09:40:53 +0100
  • 0dbee1c24c
         Merge pull request #30 from danielmlynek/make_for_riviera jrahmeh 2020-02-26 19:38:57 -0600
  • 91ac750284
         Update release-notes.md jrahmeh 2020-02-26 19:27:55 -0600
  • 7d85fc74d0
         Delete flist.riviera danielmlynek 2020-02-25 16:54:32 +0100
  • 0070c22195
         Merge branch 'master' into make_for_riviera danielmlynek 2020-02-25 16:53:53 +0100
  • 70b6f74b11
         Merge pull request #40 from olofk/fusesoc-1.5 jrahmeh 2020-02-24 15:39:31 -0600
  • cb5a7a141d
         Update dmi_jtag_to_core_sync.v jrahmeh 2020-02-24 15:00:46 -0600
  • 2a1d9be0c2
         Update dmi_jtag_to_core_sync.v jrahmeh 2020-02-24 14:52:54 -0600
  • 63e74e2391 Add initial FuseSoC support Olof Kindgren 2019-09-05 15:09:15 +0200
  • ee77552301 Version 1.5 Joseph Rahmeh 2020-02-19 18:57:15 -0800
  • cecb89057a Version 1.5 Joseph Rahmeh 2020-02-19 18:25:44 -0800
  • b65d4dd8f1 Version 1.5 Joseph Rahmeh 2020-02-19 18:25:04 -0800
  • 790c48cd0b Version 1.5 Joseph Rahmeh 2020-02-19 18:24:28 -0800
  • 36675abd25 Updated release notes. Joseph Rahmeh 2020-02-19 18:18:48 -0800
  • 480c765eb4 Cleanup release notes. Joseph Rahmeh 2020-02-19 07:07:31 -0800
  • d0c6e56012 Formatting changes. Joseph Rahmeh 2020-02-18 13:51:15 -0800
  • a44ef01adf Changed version to 1.5. Joseph Rahmeh 2020-02-18 13:41:42 -0800
  • 9228e01812 Added release notes for version 1.5. Joseph Rahmeh 2020-02-18 13:40:11 -0800
  • e57b032cd7 makefile updated for ALDECs riviera danielm 2019-12-12 08:46:21 +0100
  • 6ca86d86a9 makefile updated for ALDECs riviera danielm 2019-12-12 08:45:34 +0100
  • 1651bdf99a
         Merge pull request #29 from arupde171/master aprnath 2019-12-06 17:50:19 -0500
  • aa2bc2269d Fixed FPGA build error Arup De 2019-12-06 09:50:38 -0800
  • c89f6b7511
         Update README.md Arup De 2019-11-20 11:02:15 -0800
  • 9840fabd5c
         Added SweRV CoreMark document Arup De 2019-11-20 10:39:09 -0800
  • fb5ebdea26 Add Verilator to the PATH Todd Strader 2019-10-16 17:47:14 -0400
  • 51b8e54ff6 Add Travis CI Todd Strader 2019-10-16 16:55:27 -0400
  • 3820e84e20 Move declarations to top of Verilog file to fix fpga compile issues. Joseph Rahmeh 2019-10-15 13:14:36 -0700
  • 5fce5b0a26
         Update README.md aprnath 2019-09-08 11:15:25 -0400
  • cf4d56c78c Added basic commit register update trace in exec.log Ajay Nath 2019-09-08 11:13:17 -0400
  • 761e69df4e
         Update release-notes.md aprnath 2019-09-04 17:44:15 -0400
  • 811e9c3d24 Change clock header instance name in beh_lib.sv Joseph Rahmeh 2019-09-04 14:39:10 -0700
  • 35bc589b09 Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV Joseph Rahmeh 2019-09-04 13:32:48 -0700
  • b35d7e9e1b Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module. Joseph Rahmeh 2019-09-04 13:29:39 -0700
  • fc331027c2 Conditioned declaration of finished per issue #13 Ajay Nath 2019-09-03 21:35:43 -0400
  • 2108e722c8 Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV tmw-wdc 2019-08-13 15:48:48 -0700
  • 68f4383d96 Update RISC-V SweRV EH1 PRM.pdf tmw-wdc 2019-08-13 15:48:28 -0700
  • 4e161e6c3b Minor cleanup in config script. Joseph Rahmeh 2019-08-13 15:47:53 -0700
  • 189ce25027
         Updated release notes jrahmeh 2019-08-13 16:42:26 -0500
  • 8242950a58
         Fixed branch numbers jrahmeh 2019-08-13 15:30:00 -0500
  • c5a699aa40
         Fixed release notes jrahmeh 2019-08-13 15:08:45 -0500
  • d9bb036633 Updated hello world message. Updated last compilation time. Joseph Rahmeh 2019-08-13 12:57:04 -0700
  • 7ff8d7fb5a Untabified files. Joseph Rahmeh 2019-08-13 12:48:48 -0700