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166 Commits

Author SHA1 Message Date
Clifford Wolf 36cdf83b3f Added "make clean" handling of riscv-gnu-toolchain-riscv32* directories 2016-04-09 12:51:50 +02:00
Clifford Wolf 579b60aef9 Added "make build-riscv32i-tools" and friends 2016-04-09 12:29:19 +02:00
Clifford Wolf d657e732c6 Updated riscv-gnu-toolchain version 2016-04-09 00:17:00 +02:00
Clifford Wolf cb0f9df0d0 Added c_ebreak support to riscv-isa-sim-sbreak.diff 2016-04-08 21:41:32 +02:00
Clifford Wolf b40f5864c1 Batch processing for scripts/torture/ 2016-04-08 17:02:41 +02:00
Clifford Wolf 33c0aaf5de Single test support in scripts/torture/ 2016-04-08 16:08:23 +02:00
Clifford Wolf 548abd6cce Added scripts/torture for riscv-torture tests 2016-04-06 16:38:57 +02:00
Clifford Wolf c564a6fa87 Updated riscv-gnu-toolchain version 2016-04-06 12:08:08 +02:00
Clifford Wolf 3ccbf6877e Added mem_wstrb documentation 2016-04-03 17:14:07 +02:00
Clifford Wolf cceed2fbdf Merge pull request #5 from neuschaefer/dev 
README.md: Document the meaning of mem_instr
 2016-04-03 17:07:45 +02:00
Jonathan Neuschäfer 3217152c1b README.md: Document the meaning of mem_instr 2016-04-03 15:03:45 +02:00
Clifford Wolf e630bedda4 Merge branch 'refactoring' 2016-03-02 12:52:06 +01:00
Clifford Wolf 714f7d9cfa Merged axi4_memory.v and picorv32_wrapper.v back into testbench.v 2016-03-02 12:50:52 +01:00
Olof Kindgren cd5d341e89 Add option to load alternative firmware with plusarg 2016-02-18 22:47:58 +01:00
Olof Kindgren 9591ae9f7d Split out verilator-incompatible code to top-level testbench 
Verilator doesn't handle verilog code that deals with time, such
as delayed signals or the repeat task. Clock and reset generation
are therefore moved to a separate file that can be replaced by
a verilator module. VCD generation is also affected by this.
 2016-02-18 22:47:15 +01:00
Olof Kindgren 8343315aa7 Break out AXI4 memory to a separate module 
This commit also adds support for setting the AXI_TEST and VERBOSE
defines as plusargs or parameters
 2016-02-18 21:26:18 +01:00
Clifford Wolf c4c477180e Merged various testbench changes from compressed ISA branch 2016-02-03 16:33:01 +01:00
Clifford Wolf b1a24f4f89 minor README changes 2016-01-21 12:06:28 +01:00
Clifford Wolf 45d117fb87 Added ENABLE_FASTIRQ switch in start.S 2016-01-21 11:58:38 +01:00
Clifford Wolf 56ea35cc22 Updated riscv-gnu-toolchain 2016-01-21 11:39:24 +01:00
Clifford Wolf d2e20edaab Cleanup regarding pcpi_timeout 2015-12-22 11:17:24 +01:00
Clifford Wolf 649144ba5d Keep mem_wstrb low even when mem_valid is low anyways 2015-12-22 11:17:11 +01:00
Clifford Wolf 6e6aeaeab6 Bump riscv-gnu-toolchain version 2015-12-16 15:36:15 +01:00
Clifford Wolf 473ff0d700 Extended c++ demo 2015-12-01 15:45:37 +01:00
Clifford Wolf f2566561b0 Bump riscv-gnu-toolchain version 2015-12-01 10:49:58 +01:00
Clifford Wolf 014b2c6f09 Bugfix in hex8tohex32.py 2015-11-18 12:52:56 +01:00
Clifford Wolf aa25e426be Added hex8tohex32.py script to cxxdemo 2015-11-17 14:22:19 +01:00
Clifford Wolf c59b0043c4 Bump riscv-gnu-toolchain version 2015-11-09 11:18:12 +01:00
Clifford Wolf 4015d4a5ab Added scripts/cxxdemo/ 2015-11-04 12:55:33 +01:00
Clifford Wolf 8d9f048785 Using riscv32-unknown-elf- toolchain 2015-11-03 18:59:12 +01:00
Clifford Wolf 17a665913e dhrystone: copy&paste newlib code for memcpy() and strcpy() 2015-10-30 21:42:13 +01:00
Clifford Wolf 89abd9a957 Improvements in firmware/sections.lds 2015-10-30 15:58:29 +01:00
Clifford Wolf 3cb910cd51 Added regions to firmware/sections.lds 2015-10-30 15:52:40 +01:00
Clifford Wolf 51a9a9357a Added scripts/yosys-cmp/ 2015-10-30 14:25:04 +01:00
Clifford Wolf 8eaeebf486 Progress in "make check" 2015-10-15 15:45:19 +02:00
Clifford Wolf 07f28068f6 Added "make check" 2015-10-14 23:26:04 +02:00
Clifford Wolf 6783abd994 Merge branch 'master' of github.com:cliffordwolf/picorv32 2015-10-13 11:06:40 +02:00
Larry Doolittle f5eb93ff9d Add a missing dependency 2015-10-13 11:06:11 +02:00
Clifford Wolf a1b0d36432 Minor scripts/icestorm changes 2015-10-08 11:58:59 +02:00
Clifford Wolf 39b01ae24f Added apt-get doc for toolchain build 2015-10-07 21:22:59 +02:00
Clifford Wolf b5b1816101 Better "steps" default in smt2-bmc/sync.py 2015-10-06 11:35:23 +02:00
Clifford Wolf f8c96d6d37 Fixed README typo 2015-09-23 08:07:00 +02:00
Clifford Wolf e063f64ea2 Improvements to smtio.py 2015-09-18 20:19:14 +02:00
Clifford Wolf 482b2299d5 Updated toolchain build instructions to riscv-gnu-toolchain git 572033b 2015-09-14 12:17:26 +02:00
Clifford Wolf 00844092ee Added scripts/yosys/synth_gates 2015-09-12 14:02:23 +02:00
Clifford Wolf 686289adc5 Improvements in smtio.py 2015-08-28 00:59:12 +02:00
Clifford Wolf 534ea17811 Improvements in smtio.py "timer display during solving" feature 2015-08-28 00:12:45 +02:00
Clifford Wolf 3512605052 Added smtio.py "timer display during solving" feature 2015-08-27 22:25:11 +02:00
Clifford Wolf ebb0ea6f7b Added mkvcd class to smtio.py 2015-08-27 13:44:53 +02:00
Clifford Wolf 4b62d4cbb9 Added (set-info ..) generation to smtio.py 2015-08-27 12:46:02 +02:00