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174 Commits

Author SHA1 Message Date
Clifford Wolf 436544ccab Fix decoding of C.ADDI instruction 
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts
for discussion. There was a bug in the ISA manual.
 2017-05-13 12:28:54 +02:00
Clifford Wolf cd30db3425 Add riscv-formal alu/regs blackboxing 2017-05-11 00:13:01 +02:00
Clifford Wolf bf9687028d Fix decoding of illegal/reserved opcodes as other valid opcodes 2017-05-07 21:13:46 +02:00
Antony Pavlov 7c852571f0 testbench_wb.v: unify verbose output with axi testbench 
Unification of testbench output makes it possible to use the diff
utility for comparing testbench instruction traces.

Alas the testbench and testbench_wb traces are differ
because of interrupts, e.g.

    picorv32$ make testbench_wb.vvp
    iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v
    chmod -x testbench_wb.vvp
    picorv32$ make testbench.vvp
    iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v
    chmod -x testbench.vvp
    picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log
    picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log
    picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log
    --- /tmp/testbench.log  2017-04-06 06:56:06.079804549 +0300
    +++ /tmp/testbench_wb.log       2017-04-06 06:55:58.763485130 +0300
    @@ -850,7 +850,7 @@
     RD: ADDR=000056a0 DATA=00000013 INSN
     RD: ADDR=000056a4 DATA=fff00113 INSN
     RD: ADDR=000056a8 DATA=00000013 INSN
    -RD: ADDR=000056ac DATA=14208463 INSN  <--- testbench: no interrupt
    -RD: ADDR=000056b0 DATA=00120213 INSN
    -RD: ADDR=000056b4 DATA=00200293 INSN
    -RD: ADDR=000056b8 DATA=fe5212e3 INSN
    +RD: ADDR=00000010 DATA=0200a10b INSN  <--- testbench_wb: interrupt
    +RD: ADDR=00000014 DATA=0201218b INSN
    +RD: ADDR=00000018 DATA=000000b7 INSN
    +RD: ADDR=0000001c DATA=16008093 INSN

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-04-06 06:56:39 +03:00
Clifford Wolf 3495604877 Fix indenting in wishbone code 2017-03-14 11:51:09 +01:00
Antony Pavlov e59fa1dfb2 WIP: add WISHBONE interconnect support 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:04 +03:00
Clifford Wolf f33ddd3654 Fix in rvfi_mem_ handling (when compressed isa is enabled) 2017-02-27 14:21:42 +01:00
Clifford Wolf aaa9e25756 Add DEBUGNETS debug flag 2017-02-26 16:56:13 +01:00
Clifford Wolf c7cc32ed95 Fix verilog code for modelsim 2017-02-17 15:23:58 +01:00
Clifford Wolf e4312b0fab Fix "mem_xfer is used before its declaration" warning 2017-02-11 12:52:18 +01:00
Clifford Wolf a2107ed4ff Rename RVFI ports 2017-01-27 16:12:02 +01:00
Clifford Wolf f975ce1e45 Fix picorv32_axi STACKADDR default value 2017-01-15 20:34:19 +01:00
Oguz Meteer 510d4de1b1 Add STACKADDR parameter to picorv32_axi module 
Signed-off-by: Oguz Meteer <info@guztech.nl>
 2017-01-15 14:49:01 +01:00
Clifford Wolf f5d146c2f1 Added rvfi_mem interface 2016-12-20 11:49:09 +01:00
Clifford Wolf ef86b30b25 Fixed some linter warnings in picorv32.v 2016-12-15 14:03:27 +01:00
Clifford Wolf 72d6f6f72d Added rvfi_post_trap 2016-12-13 17:13:53 +01:00
Clifford Wolf 54a8e4b311 Fixed catching jumps to misaligned insn 2016-11-29 18:36:05 +01:00
Clifford Wolf 17c7da49f4 Renamed rvfi_opcode to rvfi_insn 2016-11-28 14:56:29 +01:00
Clifford Wolf 7fc2cbd72a More RVFI bugfixes 2016-11-27 13:46:43 +01:00
Clifford Wolf fd38f876e1 Minor RVFI bugfix 2016-11-24 15:23:33 +01:00
Clifford Wolf 117586ff19 Added RISC-V Formal Interfcae (RVFI) 2016-11-23 03:02:02 +01:00
Clifford Wolf f82af97595 Another bugfix regarding compressed ISA and unaligned insns 2016-11-18 15:36:59 +01:00
Clifford Wolf 4101cfe810 Fixed the nontrivial compressed ISA bug found by tracecmp2 2016-09-16 13:15:21 +02:00
Clifford Wolf c209c016b3 More fixes related to assertpmux checks 2016-09-13 23:21:31 +02:00
Clifford Wolf 5bea3f9917 Added more asserts for the memory interface 2016-09-13 19:34:14 +02:00
Clifford Wolf 2f3e3a6910 Merge pull request #21 from wallclimber21/mem_wdata 
Only clock mem_wdata when necesssary
 2016-09-08 09:42:51 +02:00
Tom Verbeure 38a760daf8 Fix tabs 2016-09-07 20:34:28 -07:00
Tom Verbeure 80aa70ec2e Only clock mem_wdata when necessary 2016-09-07 20:32:32 -07:00
Clifford Wolf 44d6feba2a Using assertpmux in "make check" 2016-09-07 12:40:19 +02:00
Clifford Wolf da37498191 Two minor bugfixes 2016-09-06 19:58:03 +02:00
Clifford Wolf 7f946d0f84 Added misisng MUL_CLKGATE stage 2016-09-06 01:02:12 +02:00
Clifford Wolf 5fdee952c9 Added picorv32_pcpi_fast_mul MUL_CLKGATE 2016-09-05 22:37:52 +02:00
Clifford Wolf e45cc362a7 More picorv32_pcpi_mul timing improvements 2016-09-04 18:34:11 +02:00
Clifford Wolf e91c1422a2 Added optional FFs to picorv32_pcpi_fast_mul 2016-09-04 12:44:12 +02:00
Clifford Wolf d5b7e9e175 Minor bugfix/cleanup (mostly for formal verification) 2016-09-03 14:40:13 +02:00
Clifford Wolf c9519df01b Moved cpuregs read/write to extra always blocks 2016-08-31 11:50:07 +02:00
Clifford Wolf 82d837bf96 Be more explicit about single register file write port 2016-08-31 00:08:33 +02:00
Clifford Wolf bfba9b3eb3 Bugfix in picorv32_pcpi_fast_mul 2016-08-30 11:14:46 +02:00
Clifford Wolf b9ed4364d4 Merge branch 'fast_mul_opt' of https://github.com/wallclimber21/picorv32 2016-08-30 11:12:42 +02:00
Clifford Wolf cefe09b8d4 Minor fixes/cleanups in mul reset logic 2016-08-30 11:12:16 +02:00
Tom Verbeure 9201bff2ef Reduce rs1, rs2 from 64 to 33 bits to make life for synthesis tools easier. 2016-08-29 18:00:49 -07:00
Clifford Wolf a6210c06d4 Added picorv32_pcpi_fast_mul core 2016-08-29 23:38:05 +02:00
Clifford Wolf 90070736d6 More asserts 2016-08-29 22:44:15 +02:00
Clifford Wolf 28fe45ffe9 Added more asserts to picorv32, more smtbmc examples 2016-08-29 17:23:00 +02:00
Clifford Wolf 72158ba4a5 Some minor cleanups 2016-08-26 23:56:04 +02:00
Clifford Wolf d1d3c3c5e1 Added next gen yosys-smtbmc verification scripts 2016-08-26 23:39:39 +02:00
Clifford Wolf 98d248d2c2 Finalized tracer support 2016-08-26 14:54:27 +02:00
Clifford Wolf 7094e61af7 Added tracer support (under construction) 2016-08-25 14:15:42 +02:00
Clifford Wolf 8043c90a04 Added REGS_INIT_ZERO parameter 2016-08-24 15:20:23 +02:00
Clifford Wolf 288a043aca Fixed use-before-declaration problem with VCS 2016-06-09 11:57:23 +02:00
Clifford Wolf bf062e39ac Added STACKADDR parameter 2016-06-07 17:05:02 +02:00
Clifford Wolf f4bb91b060 RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" 2016-06-06 10:46:52 +02:00
Clifford Wolf 490a734519 Encode in q0 LSB if interrupted instruction is compressed 2016-06-01 12:39:00 +02:00
Clifford Wolf fd18475e23 Do not wait for PCPI core when handling SCALL and SBREAK 2016-06-01 11:57:04 +02:00
Steve Kerrison 38d51a3383 Deassert pcpi_valid upon asserting sbreak IRQ 
This fixes #8
 2016-05-31 19:54:16 +01:00
Clifford Wolf 63c28e4389 Update dbg_ signals synchronous to the actual launch of the new insn 2016-04-14 00:50:18 +02:00
Clifford Wolf fb3178c4b7 Fixed dbg_ signals: no latches (formal verification doesn't like latches) 2016-04-13 17:29:33 +02:00
Clifford Wolf 436f162951 Minor change in DEBUGASM output 2016-04-13 15:30:02 +02:00
Clifford Wolf faa1c1a159 Added SBREAK handling for CATCH_ILLINSN=0 2016-04-13 15:09:49 +02:00
Clifford Wolf 262a9085bb Streamlined debug signals 2016-04-13 13:49:40 +02:00
Clifford Wolf 49aef71641 Some area improvements 2016-04-13 12:27:00 +02:00
Clifford Wolf 435232eb85 Use ifdef instead of generate if so we don't confuse Vivado 2016-04-13 12:21:47 +02:00
Clifford Wolf 2c76f7d61b Added (by default disabled) register file access wires for debugging 2016-04-12 20:55:46 +02:00
Clifford Wolf 789a411ead Bugfix for CATCH_ILLINSN <-> WITH_PCPI interaction 2016-04-12 20:55:06 +02:00
Clifford Wolf e9c7ea6b5d Added ENABLE_COUNTERS64 config parameter 2016-04-12 18:04:16 +02:00
Clifford Wolf 2fdafb9c16 Added BARREL_SHIFTER config parameter 2016-04-12 17:30:31 +02:00
Clifford Wolf b41c0e723c Do not re-load a word to read the 16 bit opcode in the upper half 2016-04-11 16:48:57 +02:00
Clifford Wolf b08d9400bd Do not load next word when loading a 16 bit opcode from the upper half of a 32bit word 2016-04-11 14:32:25 +02:00
Clifford Wolf 2cab981862 Fixed signed division by zero handling 2016-04-10 17:15:17 +02:00
Clifford Wolf 00dd6ac38e Added ENABLE_DIV and picorv32_pcpi_div 2016-04-10 16:54:35 +02:00
Clifford Wolf fce9656604 Bugfix in memory interface (related to compressed ISA) 2016-04-10 13:25:28 +02:00
Clifford Wolf aa17d58784 Bugfix in C.SRAI implementation 2016-04-09 14:27:28 +02:00
Clifford Wolf ef8014eebd Bugfix in C.ADDI4SPN implementation 2016-04-09 14:09:43 +02:00
Clifford Wolf d7894ca41a Merge branch 'master' into compressed 
Conflicts:
	picorv32.v
 2016-02-03 16:21:53 +01:00
Clifford Wolf d2e20edaab Cleanup regarding pcpi_timeout 2015-12-22 11:17:24 +01:00
Clifford Wolf 649144ba5d Keep mem_wstrb low even when mem_valid is low anyways 2015-12-22 11:17:11 +01:00
Clifford Wolf 5953e57899 Towards compressed ISA support 2015-11-20 16:45:09 +01:00
Clifford Wolf f8eed23a68 Towards compressed ISA support 2015-11-19 14:01:33 +01:00
Clifford Wolf 9d5f8ad8e6 Towards compressed ISA support 2015-11-19 04:02:00 +01:00
Clifford Wolf c4e711209c Towards compressed ISA support 2015-11-18 19:23:11 +01:00
Clifford Wolf 3aed9f7c65 Towards compressed ISA support 2015-11-18 15:55:29 +01:00
Clifford Wolf 8174d8fb7e Towards compressed ISA support 2015-11-15 23:24:38 +01:00
Clifford Wolf bfd2a4e0fa Towards compressed ISA support 2015-11-15 16:04:04 +01:00
Clifford Wolf bf4b0f3a63 Towards compressed ISA support 2015-11-14 19:22:00 +01:00
Clifford Wolf 60b9216856 Towards compressed ISA support 2015-11-14 14:11:21 +01:00
Clifford Wolf db26b51afe Towards compressed ISA support 2015-11-13 14:16:32 +01:00
Clifford Wolf 8eaeebf486 Progress in "make check" 2015-10-15 15:45:19 +02:00
Clifford Wolf 07f28068f6 Added "make check" 2015-10-14 23:26:04 +02:00
Clifford Wolf 16f97a86a1 Reset bugfix (bug found via scripts/smt2-bmc/mem_equiv.*) 2015-08-13 13:30:21 +02:00
Clifford Wolf bf7f984d42 Refactoring of TWO_CYCLE_ALU 2015-07-08 23:15:14 +02:00
Clifford Wolf dd30b57ea6 Added TWO_CYCLE_ALU parameter 2015-07-08 20:17:03 +02:00
Clifford Wolf b6c4c2eeb9 Added TWO_CYCLE_COMPARE 2015-07-07 22:51:52 +02:00
Clifford Wolf 9c028fc965 Added missing LD_RS1 debug statements 2015-07-02 14:51:28 +02:00
Clifford Wolf ab503d5756 Being more aggressive with parallel cases 2015-07-02 12:55:05 +02:00
Clifford Wolf c10125eb5c Added TWO_STAGE_SHIFT parameter 2015-07-02 12:29:06 +02:00
Clifford Wolf 853ce91300 Added `debug macro 2015-07-02 12:17:45 +02:00
Clifford Wolf c48a3b2434 Removed trailing whitespaces 2015-07-02 10:49:35 +02:00
Clifford Wolf 34193bf9df Added CATCH_MISALIGN and CATCH_ILLINSN 2015-07-01 21:20:51 +02:00
Clifford Wolf f6fe27ecbf After some profiling: one-hot FSM encoding 2015-07-01 21:20:31 +02:00
Clifford Wolf 4a9fda0737 Improvements in PCPI MUL core 2015-06-30 16:51:26 +02:00