Clifford Wolf
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f975ce1e45
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Fix picorv32_axi STACKADDR default value
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2017-01-15 20:34:19 +01:00 |
Oguz Meteer
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510d4de1b1
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Add STACKADDR parameter to picorv32_axi module
Signed-off-by: Oguz Meteer <info@guztech.nl>
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2017-01-15 14:49:01 +01:00 |
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Clifford Wolf
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f5d146c2f1
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Added rvfi_mem interface
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2016-12-20 11:49:09 +01:00 |
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Clifford Wolf
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ef86b30b25
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Fixed some linter warnings in picorv32.v
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2016-12-15 14:03:27 +01:00 |
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Clifford Wolf
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72d6f6f72d
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Added rvfi_post_trap
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2016-12-13 17:13:53 +01:00 |
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Clifford Wolf
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54a8e4b311
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Fixed catching jumps to misaligned insn
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2016-11-29 18:36:05 +01:00 |
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Clifford Wolf
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17c7da49f4
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Renamed rvfi_opcode to rvfi_insn
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2016-11-28 14:56:29 +01:00 |
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Clifford Wolf
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7fc2cbd72a
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More RVFI bugfixes
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2016-11-27 13:46:43 +01:00 |
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Clifford Wolf
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fd38f876e1
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Minor RVFI bugfix
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2016-11-24 15:23:33 +01:00 |
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Clifford Wolf
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117586ff19
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Added RISC-V Formal Interfcae (RVFI)
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2016-11-23 03:02:02 +01:00 |
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Clifford Wolf
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f82af97595
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Another bugfix regarding compressed ISA and unaligned insns
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2016-11-18 15:36:59 +01:00 |
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Clifford Wolf
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4101cfe810
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Fixed the nontrivial compressed ISA bug found by tracecmp2
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2016-09-16 13:15:21 +02:00 |
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Clifford Wolf
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c209c016b3
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More fixes related to assertpmux checks
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2016-09-13 23:21:31 +02:00 |
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Clifford Wolf
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5bea3f9917
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Added more asserts for the memory interface
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2016-09-13 19:34:14 +02:00 |
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Clifford Wolf
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2f3e3a6910
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Merge pull request #21 from wallclimber21/mem_wdata
Only clock mem_wdata when necesssary
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2016-09-08 09:42:51 +02:00 |
Tom Verbeure
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38a760daf8
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Fix tabs
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2016-09-07 20:34:28 -07:00 |
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Tom Verbeure
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80aa70ec2e
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Only clock mem_wdata when necessary
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2016-09-07 20:32:32 -07:00 |
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Clifford Wolf
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44d6feba2a
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Using assertpmux in "make check"
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2016-09-07 12:40:19 +02:00 |
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Clifford Wolf
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da37498191
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Two minor bugfixes
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2016-09-06 19:58:03 +02:00 |
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Clifford Wolf
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7f946d0f84
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Added misisng MUL_CLKGATE stage
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2016-09-06 01:02:12 +02:00 |
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Clifford Wolf
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5fdee952c9
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Added picorv32_pcpi_fast_mul MUL_CLKGATE
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2016-09-05 22:37:52 +02:00 |
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Clifford Wolf
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e45cc362a7
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More picorv32_pcpi_mul timing improvements
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2016-09-04 18:34:11 +02:00 |
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Clifford Wolf
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e91c1422a2
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Added optional FFs to picorv32_pcpi_fast_mul
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2016-09-04 12:44:12 +02:00 |
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Clifford Wolf
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d5b7e9e175
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Minor bugfix/cleanup (mostly for formal verification)
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2016-09-03 14:40:13 +02:00 |
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Clifford Wolf
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c9519df01b
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Moved cpuregs read/write to extra always blocks
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2016-08-31 11:50:07 +02:00 |
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Clifford Wolf
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82d837bf96
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Be more explicit about single register file write port
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2016-08-31 00:08:33 +02:00 |
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Clifford Wolf
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bfba9b3eb3
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Bugfix in picorv32_pcpi_fast_mul
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2016-08-30 11:14:46 +02:00 |
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Clifford Wolf
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b9ed4364d4
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Merge branch 'fast_mul_opt' of https://github.com/wallclimber21/picorv32
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2016-08-30 11:12:42 +02:00 |
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Clifford Wolf
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cefe09b8d4
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Minor fixes/cleanups in mul reset logic
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2016-08-30 11:12:16 +02:00 |
|
Tom Verbeure
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9201bff2ef
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Reduce rs1, rs2 from 64 to 33 bits to make life for synthesis tools easier.
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2016-08-29 18:00:49 -07:00 |
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Clifford Wolf
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a6210c06d4
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Added picorv32_pcpi_fast_mul core
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2016-08-29 23:38:05 +02:00 |
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Clifford Wolf
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90070736d6
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More asserts
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2016-08-29 22:44:15 +02:00 |
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Clifford Wolf
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28fe45ffe9
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Added more asserts to picorv32, more smtbmc examples
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2016-08-29 17:23:00 +02:00 |
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Clifford Wolf
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72158ba4a5
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Some minor cleanups
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2016-08-26 23:56:04 +02:00 |
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Clifford Wolf
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d1d3c3c5e1
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Added next gen yosys-smtbmc verification scripts
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2016-08-26 23:39:39 +02:00 |
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Clifford Wolf
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98d248d2c2
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Finalized tracer support
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2016-08-26 14:54:27 +02:00 |
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Clifford Wolf
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7094e61af7
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Added tracer support (under construction)
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2016-08-25 14:15:42 +02:00 |
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Clifford Wolf
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8043c90a04
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Added REGS_INIT_ZERO parameter
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2016-08-24 15:20:23 +02:00 |
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Clifford Wolf
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288a043aca
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Fixed use-before-declaration problem with VCS
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2016-06-09 11:57:23 +02:00 |
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Clifford Wolf
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bf062e39ac
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Added STACKADDR parameter
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2016-06-07 17:05:02 +02:00 |
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Clifford Wolf
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f4bb91b060
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RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"
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2016-06-06 10:46:52 +02:00 |
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Clifford Wolf
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490a734519
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Encode in q0 LSB if interrupted instruction is compressed
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2016-06-01 12:39:00 +02:00 |
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Clifford Wolf
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fd18475e23
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Do not wait for PCPI core when handling SCALL and SBREAK
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2016-06-01 11:57:04 +02:00 |
Steve Kerrison
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38d51a3383
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Deassert pcpi_valid upon asserting sbreak IRQ
This fixes #8
|
2016-05-31 19:54:16 +01:00 |
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Clifford Wolf
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63c28e4389
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Update dbg_ signals synchronous to the actual launch of the new insn
|
2016-04-14 00:50:18 +02:00 |
|
Clifford Wolf
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fb3178c4b7
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Fixed dbg_ signals: no latches (formal verification doesn't like latches)
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2016-04-13 17:29:33 +02:00 |
|
Clifford Wolf
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436f162951
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Minor change in DEBUGASM output
|
2016-04-13 15:30:02 +02:00 |
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Clifford Wolf
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faa1c1a159
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Added SBREAK handling for CATCH_ILLINSN=0
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2016-04-13 15:09:49 +02:00 |
|
Clifford Wolf
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262a9085bb
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Streamlined debug signals
|
2016-04-13 13:49:40 +02:00 |
|
Clifford Wolf
|
49aef71641
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Some area improvements
|
2016-04-13 12:27:00 +02:00 |
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Clifford Wolf
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435232eb85
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Use ifdef instead of generate if so we don't confuse Vivado
|
2016-04-13 12:21:47 +02:00 |
|
Clifford Wolf
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2c76f7d61b
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Added (by default disabled) register file access wires for debugging
|
2016-04-12 20:55:46 +02:00 |
|
Clifford Wolf
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789a411ead
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Bugfix for CATCH_ILLINSN <-> WITH_PCPI interaction
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2016-04-12 20:55:06 +02:00 |
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Clifford Wolf
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e9c7ea6b5d
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Added ENABLE_COUNTERS64 config parameter
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2016-04-12 18:04:16 +02:00 |
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Clifford Wolf
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2fdafb9c16
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Added BARREL_SHIFTER config parameter
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2016-04-12 17:30:31 +02:00 |
|
Clifford Wolf
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b41c0e723c
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Do not re-load a word to read the 16 bit opcode in the upper half
|
2016-04-11 16:48:57 +02:00 |
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Clifford Wolf
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b08d9400bd
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Do not load next word when loading a 16 bit opcode from the upper half of a 32bit word
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2016-04-11 14:32:25 +02:00 |
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Clifford Wolf
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2cab981862
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Fixed signed division by zero handling
|
2016-04-10 17:15:17 +02:00 |
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Clifford Wolf
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00dd6ac38e
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Added ENABLE_DIV and picorv32_pcpi_div
|
2016-04-10 16:54:35 +02:00 |
|
Clifford Wolf
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fce9656604
|
Bugfix in memory interface (related to compressed ISA)
|
2016-04-10 13:25:28 +02:00 |
|
Clifford Wolf
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aa17d58784
|
Bugfix in C.SRAI implementation
|
2016-04-09 14:27:28 +02:00 |
|
Clifford Wolf
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ef8014eebd
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Bugfix in C.ADDI4SPN implementation
|
2016-04-09 14:09:43 +02:00 |
|
Clifford Wolf
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d7894ca41a
|
Merge branch 'master' into compressed
Conflicts:
picorv32.v
|
2016-02-03 16:21:53 +01:00 |
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Clifford Wolf
|
d2e20edaab
|
Cleanup regarding pcpi_timeout
|
2015-12-22 11:17:24 +01:00 |
|
Clifford Wolf
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649144ba5d
|
Keep mem_wstrb low even when mem_valid is low anyways
|
2015-12-22 11:17:11 +01:00 |
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Clifford Wolf
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5953e57899
|
Towards compressed ISA support
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2015-11-20 16:45:09 +01:00 |
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Clifford Wolf
|
f8eed23a68
|
Towards compressed ISA support
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2015-11-19 14:01:33 +01:00 |
|
Clifford Wolf
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9d5f8ad8e6
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Towards compressed ISA support
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2015-11-19 04:02:00 +01:00 |
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Clifford Wolf
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c4e711209c
|
Towards compressed ISA support
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2015-11-18 19:23:11 +01:00 |
|
Clifford Wolf
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3aed9f7c65
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Towards compressed ISA support
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2015-11-18 15:55:29 +01:00 |
|
Clifford Wolf
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8174d8fb7e
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Towards compressed ISA support
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2015-11-15 23:24:38 +01:00 |
|
Clifford Wolf
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bfd2a4e0fa
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Towards compressed ISA support
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2015-11-15 16:04:04 +01:00 |
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Clifford Wolf
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bf4b0f3a63
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Towards compressed ISA support
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2015-11-14 19:22:00 +01:00 |
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Clifford Wolf
|
60b9216856
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Towards compressed ISA support
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2015-11-14 14:11:21 +01:00 |
|
Clifford Wolf
|
db26b51afe
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Towards compressed ISA support
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2015-11-13 14:16:32 +01:00 |
|
Clifford Wolf
|
8eaeebf486
|
Progress in "make check"
|
2015-10-15 15:45:19 +02:00 |
|
Clifford Wolf
|
07f28068f6
|
Added "make check"
|
2015-10-14 23:26:04 +02:00 |
|
Clifford Wolf
|
16f97a86a1
|
Reset bugfix (bug found via scripts/smt2-bmc/mem_equiv.*)
|
2015-08-13 13:30:21 +02:00 |
|
Clifford Wolf
|
bf7f984d42
|
Refactoring of TWO_CYCLE_ALU
|
2015-07-08 23:15:14 +02:00 |
|
Clifford Wolf
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dd30b57ea6
|
Added TWO_CYCLE_ALU parameter
|
2015-07-08 20:17:03 +02:00 |
|
Clifford Wolf
|
b6c4c2eeb9
|
Added TWO_CYCLE_COMPARE
|
2015-07-07 22:51:52 +02:00 |
|
Clifford Wolf
|
9c028fc965
|
Added missing LD_RS1 debug statements
|
2015-07-02 14:51:28 +02:00 |
|
Clifford Wolf
|
ab503d5756
|
Being more aggressive with parallel cases
|
2015-07-02 12:55:05 +02:00 |
|
Clifford Wolf
|
c10125eb5c
|
Added TWO_STAGE_SHIFT parameter
|
2015-07-02 12:29:06 +02:00 |
|
Clifford Wolf
|
853ce91300
|
Added `debug macro
|
2015-07-02 12:17:45 +02:00 |
|
Clifford Wolf
|
c48a3b2434
|
Removed trailing whitespaces
|
2015-07-02 10:49:35 +02:00 |
|
Clifford Wolf
|
34193bf9df
|
Added CATCH_MISALIGN and CATCH_ILLINSN
|
2015-07-01 21:20:51 +02:00 |
|
Clifford Wolf
|
f6fe27ecbf
|
After some profiling: one-hot FSM encoding
|
2015-07-01 21:20:31 +02:00 |
|
Clifford Wolf
|
4a9fda0737
|
Improvements in PCPI MUL core
|
2015-06-30 16:51:26 +02:00 |
|
Clifford Wolf
|
7417a3e249
|
Added LATCHED_IRQ parameter
|
2015-06-29 07:54:47 +02:00 |
|
Clifford Wolf
|
46026ba985
|
Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMER
|
2015-06-28 22:09:51 +02:00 |
|
Clifford Wolf
|
21157b8f1d
|
Cleanups in PCPI interface
|
2015-06-28 15:41:55 +02:00 |
|
Clifford Wolf
|
b076d72806
|
Fixed PCPI instr prefetching
|
2015-06-28 14:51:53 +02:00 |
|
Clifford Wolf
|
1f99de5117
|
Improvements in picorv32_pcpi_mul
|
2015-06-28 13:07:50 +02:00 |
|
Clifford Wolf
|
4c15e05298
|
Moved ENABLE_MUL from picorv32_axi to picorv32
|
2015-06-28 12:19:49 +02:00 |
|
Clifford Wolf
|
034e1a6af7
|
Added PCPI to picorv32_axi
|
2015-06-27 23:54:11 +02:00 |
|
Clifford Wolf
|
7d1a484812
|
Implemented picorv32_pcpi_mul
|
2015-06-27 23:53:51 +02:00 |
|
Clifford Wolf
|
dd8ed3c877
|
Added pcpi_wait interface
|
2015-06-26 23:48:50 +02:00 |
|
Clifford Wolf
|
0be990bd04
|
Added Pico Co-Processor Interface (PCPI)
|
2015-06-26 23:15:35 +02:00 |
|
Clifford Wolf
|
5d4ce82050
|
Implemented waitirq instruction
|
2015-06-26 10:39:08 +02:00 |