Clifford Wolf
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288a043aca
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Fixed use-before-declaration problem with VCS
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2016-06-09 11:57:23 +02:00 |
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Clifford Wolf
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bf062e39ac
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Added STACKADDR parameter
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2016-06-07 17:05:02 +02:00 |
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Clifford Wolf
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f4bb91b060
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RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"
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2016-06-06 10:46:52 +02:00 |
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Clifford Wolf
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490a734519
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Encode in q0 LSB if interrupted instruction is compressed
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2016-06-01 12:39:00 +02:00 |
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Clifford Wolf
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fd18475e23
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Do not wait for PCPI core when handling SCALL and SBREAK
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2016-06-01 11:57:04 +02:00 |
Steve Kerrison
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38d51a3383
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Deassert pcpi_valid upon asserting sbreak IRQ
This fixes #8
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2016-05-31 19:54:16 +01:00 |
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Clifford Wolf
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63c28e4389
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Update dbg_ signals synchronous to the actual launch of the new insn
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2016-04-14 00:50:18 +02:00 |
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Clifford Wolf
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fb3178c4b7
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Fixed dbg_ signals: no latches (formal verification doesn't like latches)
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2016-04-13 17:29:33 +02:00 |
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Clifford Wolf
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436f162951
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Minor change in DEBUGASM output
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2016-04-13 15:30:02 +02:00 |
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Clifford Wolf
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faa1c1a159
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Added SBREAK handling for CATCH_ILLINSN=0
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2016-04-13 15:09:49 +02:00 |
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Clifford Wolf
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262a9085bb
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Streamlined debug signals
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2016-04-13 13:49:40 +02:00 |
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Clifford Wolf
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49aef71641
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Some area improvements
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2016-04-13 12:27:00 +02:00 |
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Clifford Wolf
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435232eb85
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Use ifdef instead of generate if so we don't confuse Vivado
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2016-04-13 12:21:47 +02:00 |
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Clifford Wolf
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2c76f7d61b
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Added (by default disabled) register file access wires for debugging
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2016-04-12 20:55:46 +02:00 |
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Clifford Wolf
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789a411ead
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Bugfix for CATCH_ILLINSN <-> WITH_PCPI interaction
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2016-04-12 20:55:06 +02:00 |
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Clifford Wolf
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e9c7ea6b5d
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Added ENABLE_COUNTERS64 config parameter
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2016-04-12 18:04:16 +02:00 |
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Clifford Wolf
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2fdafb9c16
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Added BARREL_SHIFTER config parameter
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2016-04-12 17:30:31 +02:00 |
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Clifford Wolf
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b41c0e723c
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Do not re-load a word to read the 16 bit opcode in the upper half
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2016-04-11 16:48:57 +02:00 |
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Clifford Wolf
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b08d9400bd
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Do not load next word when loading a 16 bit opcode from the upper half of a 32bit word
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2016-04-11 14:32:25 +02:00 |
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Clifford Wolf
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2cab981862
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Fixed signed division by zero handling
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2016-04-10 17:15:17 +02:00 |
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Clifford Wolf
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00dd6ac38e
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Added ENABLE_DIV and picorv32_pcpi_div
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2016-04-10 16:54:35 +02:00 |
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Clifford Wolf
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fce9656604
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Bugfix in memory interface (related to compressed ISA)
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2016-04-10 13:25:28 +02:00 |
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Clifford Wolf
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aa17d58784
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Bugfix in C.SRAI implementation
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2016-04-09 14:27:28 +02:00 |
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Clifford Wolf
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ef8014eebd
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Bugfix in C.ADDI4SPN implementation
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2016-04-09 14:09:43 +02:00 |
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Clifford Wolf
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d7894ca41a
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Merge branch 'master' into compressed
Conflicts:
picorv32.v
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2016-02-03 16:21:53 +01:00 |
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Clifford Wolf
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d2e20edaab
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Cleanup regarding pcpi_timeout
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2015-12-22 11:17:24 +01:00 |
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Clifford Wolf
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649144ba5d
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Keep mem_wstrb low even when mem_valid is low anyways
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2015-12-22 11:17:11 +01:00 |
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Clifford Wolf
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5953e57899
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Towards compressed ISA support
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2015-11-20 16:45:09 +01:00 |
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Clifford Wolf
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f8eed23a68
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Towards compressed ISA support
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2015-11-19 14:01:33 +01:00 |
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Clifford Wolf
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9d5f8ad8e6
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Towards compressed ISA support
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2015-11-19 04:02:00 +01:00 |
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Clifford Wolf
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c4e711209c
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Towards compressed ISA support
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2015-11-18 19:23:11 +01:00 |
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Clifford Wolf
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3aed9f7c65
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Towards compressed ISA support
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2015-11-18 15:55:29 +01:00 |
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Clifford Wolf
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8174d8fb7e
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Towards compressed ISA support
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2015-11-15 23:24:38 +01:00 |
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Clifford Wolf
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bfd2a4e0fa
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Towards compressed ISA support
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2015-11-15 16:04:04 +01:00 |
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Clifford Wolf
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bf4b0f3a63
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Towards compressed ISA support
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2015-11-14 19:22:00 +01:00 |
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Clifford Wolf
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60b9216856
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Towards compressed ISA support
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2015-11-14 14:11:21 +01:00 |
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Clifford Wolf
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db26b51afe
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Towards compressed ISA support
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2015-11-13 14:16:32 +01:00 |
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Clifford Wolf
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8eaeebf486
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Progress in "make check"
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2015-10-15 15:45:19 +02:00 |
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Clifford Wolf
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07f28068f6
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Added "make check"
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2015-10-14 23:26:04 +02:00 |
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Clifford Wolf
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16f97a86a1
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Reset bugfix (bug found via scripts/smt2-bmc/mem_equiv.*)
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2015-08-13 13:30:21 +02:00 |
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Clifford Wolf
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bf7f984d42
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Refactoring of TWO_CYCLE_ALU
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2015-07-08 23:15:14 +02:00 |
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Clifford Wolf
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dd30b57ea6
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Added TWO_CYCLE_ALU parameter
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2015-07-08 20:17:03 +02:00 |
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Clifford Wolf
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b6c4c2eeb9
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Added TWO_CYCLE_COMPARE
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2015-07-07 22:51:52 +02:00 |
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Clifford Wolf
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9c028fc965
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Added missing LD_RS1 debug statements
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2015-07-02 14:51:28 +02:00 |
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Clifford Wolf
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ab503d5756
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Being more aggressive with parallel cases
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2015-07-02 12:55:05 +02:00 |
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Clifford Wolf
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c10125eb5c
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Added TWO_STAGE_SHIFT parameter
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2015-07-02 12:29:06 +02:00 |
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Clifford Wolf
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853ce91300
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Added `debug macro
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2015-07-02 12:17:45 +02:00 |
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Clifford Wolf
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c48a3b2434
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Removed trailing whitespaces
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2015-07-02 10:49:35 +02:00 |
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Clifford Wolf
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34193bf9df
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Added CATCH_MISALIGN and CATCH_ILLINSN
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2015-07-01 21:20:51 +02:00 |
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Clifford Wolf
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f6fe27ecbf
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After some profiling: one-hot FSM encoding
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2015-07-01 21:20:31 +02:00 |
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Clifford Wolf
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4a9fda0737
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Improvements in PCPI MUL core
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2015-06-30 16:51:26 +02:00 |
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Clifford Wolf
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7417a3e249
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Added LATCHED_IRQ parameter
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2015-06-29 07:54:47 +02:00 |
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Clifford Wolf
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46026ba985
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Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMER
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2015-06-28 22:09:51 +02:00 |
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Clifford Wolf
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21157b8f1d
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Cleanups in PCPI interface
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2015-06-28 15:41:55 +02:00 |
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Clifford Wolf
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b076d72806
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Fixed PCPI instr prefetching
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2015-06-28 14:51:53 +02:00 |
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Clifford Wolf
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1f99de5117
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Improvements in picorv32_pcpi_mul
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2015-06-28 13:07:50 +02:00 |
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Clifford Wolf
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4c15e05298
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Moved ENABLE_MUL from picorv32_axi to picorv32
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2015-06-28 12:19:49 +02:00 |
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Clifford Wolf
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034e1a6af7
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Added PCPI to picorv32_axi
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2015-06-27 23:54:11 +02:00 |
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Clifford Wolf
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7d1a484812
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Implemented picorv32_pcpi_mul
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2015-06-27 23:53:51 +02:00 |
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Clifford Wolf
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dd8ed3c877
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Added pcpi_wait interface
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2015-06-26 23:48:50 +02:00 |
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Clifford Wolf
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0be990bd04
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Added Pico Co-Processor Interface (PCPI)
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2015-06-26 23:15:35 +02:00 |
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Clifford Wolf
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5d4ce82050
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Implemented waitirq instruction
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2015-06-26 10:39:08 +02:00 |
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Clifford Wolf
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9a4a06d981
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Refactoring of IRQ handling
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2015-06-26 10:03:37 +02:00 |
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Clifford Wolf
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23b700cf73
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Added basic IRQ support
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2015-06-25 14:08:39 +02:00 |
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Clifford Wolf
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bb7f500489
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Removed unnecessary "jal" complexity
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2015-06-09 07:40:30 +02:00 |
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Clifford Wolf
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a9532f81ed
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Refactored instruction decoder
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2015-06-08 09:08:19 +02:00 |
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Clifford Wolf
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32208c0b70
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Improved timing for "decoded_imm_uj"
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2015-06-07 22:50:49 +02:00 |
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Clifford Wolf
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34d9dea8c7
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Added support for dual-port register file
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2015-06-07 20:53:19 +02:00 |
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Clifford Wolf
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60867e10a9
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minor optimizations
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2015-06-07 20:08:04 +02:00 |
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Clifford Wolf
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8e3e0bfba0
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Improved "decoder_trigger" handling
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2015-06-07 19:49:38 +02:00 |
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Clifford Wolf
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bbbcea2faa
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Added look-ahead write interface
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2015-06-07 12:11:20 +02:00 |
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Clifford Wolf
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e84f044bc5
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Major redesign of main FSM
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2015-06-07 11:49:47 +02:00 |
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Clifford Wolf
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bc8ffd2ecb
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Added memory "look-ahead" read interface
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2015-06-06 20:50:53 +02:00 |
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Clifford Wolf
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7fd24a96b2
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Improved AXI Interface Testbench
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2015-06-06 17:15:09 +02:00 |
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Clifford Wolf
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77ba5a1897
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Initial import
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2015-06-06 14:14:32 +02:00 |