Colin
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c6d2b351df
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Change clock from 12 to 25.
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2025-04-06 19:47:55 +08:00 |
|
Colin
|
3255e9e952
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Pass ECP5 fpga and jlink debug core.
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2025-04-02 10:41:27 +08:00 |
|
Colin
|
2e649e2c86
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Add softuart to soc_cxxrtl test.
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2025-03-30 18:36:35 +08:00 |
|
Colin
|
aaad0d85a5
|
Enable aph port off soc, and print prints.
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2025-03-27 23:48:10 +08:00 |
Luke Wren
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9c56e669cd
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Standardise on a single ISA variant for default test builds, and align this with the lightweight toolchain config in the Readme
(Automated test builds for multiple ISA variants still yet to be implemented)
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2024-08-07 13:34:36 -07:00 |
|
Luke Wren
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5aee830ac0
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Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
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2023-03-31 01:53:28 +01:00 |
|
Luke Wren
|
e966e832d2
|
First attempt at Zcmp
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2023-03-20 00:19:23 +00:00 |
|
Luke Wren
|
ef35dc859d
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Add zicsr to march in makefiles
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2022-05-24 16:17:54 +01:00 |
|
Luke Wren
|
6fcc74a043
|
Add some instructions to Readme
|
2021-07-24 11:53:08 +01:00 |
|
Luke Wren
|
c03bc2efb5
|
Update init.S for new IRQ functionality
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2021-06-04 08:16:54 +01:00 |
|
Luke Wren
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90acfdcbe8
|
Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |