Luke Wren
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460fa0bb4a
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Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
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2022-05-28 17:22:28 +01:00 |
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Luke Wren
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66965ac073
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Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
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2022-05-28 15:36:21 +01:00 |
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Luke Wren
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4090f4eb24
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Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
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2022-05-28 15:01:27 +01:00 |
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Luke Wren
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9e2f5df00a
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Add testbench flag to propagate CPU return code to testbench return
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2022-05-28 15:00:28 +01:00 |
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Luke Wren
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81aec325bb
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ecall from U-mode has a different mcause value than ecall from M-mode
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2022-05-28 12:07:29 +01:00 |
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Luke Wren
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632c61daba
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Rebase debug tests, pick up two new tests (both pass)
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2022-05-28 11:34:41 +01:00 |
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Luke Wren
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f2876eb51f
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Fix bad mepc reported after branching to a branch in a no-X address range
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2022-05-27 22:47:04 +01:00 |
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Luke Wren
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b655148148
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Bump riscv-tests for better PMP disable fix
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2022-05-27 21:36:54 +01:00 |
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Luke Wren
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e208652ad7
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Fix misa value in csr_id test
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2022-05-26 00:48:12 +01:00 |
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Luke Wren
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d7787942e9
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Add two new tests to debug test list. Remainder are still non-applicable
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2022-05-26 00:47:08 +01:00 |
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Luke Wren
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a17b941e38
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Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
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2022-05-25 23:46:23 +01:00 |
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Luke Wren
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37f7588bad
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Fix hazard3 reset vector check value in debug tests
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2022-05-25 21:45:36 +01:00 |
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Luke Wren
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5be8835365
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Add missing output to pmp_write_and_lock test
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2022-05-25 15:34:28 +01:00 |
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Luke Wren
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399dcf2cb9
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Add test for U-mode X permissions
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2022-05-25 13:47:16 +01:00 |
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Luke Wren
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7340765699
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Add simple test to read, write and lock PMP registers
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2022-05-25 02:05:24 +01:00 |
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Luke Wren
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456810b09e
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Make vcd generation optional in runtests
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2022-05-24 22:56:13 +01:00 |
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Luke Wren
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64d9f4a111
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Add tests for execution of mret and wfi in U mode
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2022-05-24 22:14:20 +01:00 |
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Luke Wren
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20f06c4a02
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Build tb with 4 PMP regions by default
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2022-05-24 20:06:57 +01:00 |
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Luke Wren
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7cfc976ef2
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Set U RWX permission on all of memory in the U CSR readability test
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2022-05-24 19:58:12 +01:00 |
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Luke Wren
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cfed35b3da
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Fix the stupid printf warning on x86-64 as well as arm64
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2022-05-24 18:22:25 +01:00 |
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Luke Wren
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f033cde874
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Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
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2022-05-24 17:30:24 +01:00 |
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Luke Wren
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ba81b533d2
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Build core with U mode support for tb
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2022-05-24 16:44:22 +01:00 |
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Luke Wren
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0199f48087
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Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
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2022-05-24 16:44:03 +01:00 |
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Luke Wren
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4ba3f7ceb9
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Fix format warning in tb.cpp on arm64
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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ef35dc859d
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Add zicsr to march in makefiles
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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07d4b23a9a
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Add option to pass test list to runtests
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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31061bd472
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Add Zbkb to bitmanip tests and regenerate vectors
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2022-05-21 17:15:46 +01:00 |
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Luke Wren
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4ffe007a84
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Add zicsr to march in bitmanip tests, so it builds on newer toolchains
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2022-05-20 01:32:21 +01:00 |
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Luke Wren
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7dc5046505
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Perf option for dedicated branch comparator
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2022-04-02 11:40:47 +01:00 |
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Luke Wren
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3c61fae9ef
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Remove the halfword fetch thing, was only really useful on RISCBoy
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2022-04-02 10:54:16 +01:00 |
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Luke Wren
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5aca1381ac
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Couple of fixups for rvpy which I forgot to commit at some point
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2022-03-01 20:27:18 +00:00 |
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Luke Wren
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28b53ef7b5
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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Luke Wren
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a81d129961
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Add exclusives monitor to testbench
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2021-12-17 17:03:35 +00:00 |
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Luke Wren
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5ab60422ad
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Add minimal multicore launch code
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2021-12-17 01:24:11 +00:00 |
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Luke Wren
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01d9617f9c
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Add multicore tb integration file
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2021-12-17 00:41:23 +00:00 |
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Luke Wren
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207566660d
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tb: handle both ports identically. Preparing for dual core
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2021-12-17 00:04:00 +00:00 |
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Luke Wren
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88fea7acfa
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Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
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2021-12-12 18:28:23 +00:00 |
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Luke Wren
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719c21fec3
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Add IRQ tests. Disable waves by default in runtests
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2021-12-12 15:53:04 +00:00 |
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Luke Wren
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9fb2af800f
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Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
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2021-12-12 14:58:50 +00:00 |
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Luke Wren
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a232833d81
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Add CSR writable test
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2021-12-12 14:23:34 +00:00 |
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Luke Wren
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8a003dbbed
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Make mcycle/minstret inhibited by default
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2021-12-12 13:55:33 +00:00 |
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Luke Wren
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7da67a0600
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Similarly for minstret
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2021-12-11 22:25:12 +00:00 |
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Luke Wren
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1b722b5f27
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Add mcycle test, fix incorrect description of mcycle in docs
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2021-12-11 21:21:31 +00:00 |
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Luke Wren
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93eca19aeb
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Add test for lr/sc RAW stalls
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2021-12-11 19:16:41 +00:00 |
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Luke Wren
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763a5cd364
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Add test for readability of all implemented CSRs
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2021-12-11 17:50:12 +00:00 |
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Luke Wren
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7b1da32af1
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Move expected_output into tests inline
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2021-12-11 16:58:25 +00:00 |
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Luke Wren
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9460b3cd04
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Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
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2021-12-11 15:52:34 +00:00 |
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Luke Wren
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f64f44f7af
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Add test for identification CSRs vs expected values
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2021-12-11 13:26:59 +00:00 |
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Luke Wren
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4066e941ef
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Fix sim cmdline in bitmanip-random tests
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2021-12-11 13:13:21 +00:00 |
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Luke Wren
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3fe0d92d41
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Add load/store alignment testcases
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2021-12-11 12:53:37 +00:00 |