Luke Wren
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489480dc80
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Revise default config values, and update docs with new values
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2022-10-08 08:43:25 +01:00 |
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Luke Wren
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874cb20910
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Add config headers to tb_cxxrtl instead of using defparams in Makefile
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2022-10-08 08:09:26 +01:00 |
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Luke Wren
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e6aaf4b801
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Avoid IRQ to bus through-path when custom IRQs are disabled
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2022-10-06 00:16:10 +01:00 |
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Luke Wren
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c55d3f0d0b
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Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.
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2022-10-05 23:53:04 +01:00 |
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Luke Wren
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2ae2463b97
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First stab at adding wake/sleep state machine
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2022-08-28 19:50:04 +01:00 |
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Luke Wren
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6e3799eed0
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First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
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2022-08-22 08:47:03 +01:00 |
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Luke Wren
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15cb21ae43
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First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
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2022-08-07 20:51:12 +01:00 |
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Luke Wren
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185194973f
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Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
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2022-08-06 23:02:08 +01:00 |
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Luke Wren
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b7d9defcf2
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Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
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2022-07-05 03:37:19 +01:00 |
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Luke Wren
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0766ec6f8a
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First pass at adding branch prediction
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2022-06-15 02:05:46 +01:00 |
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Luke Wren
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ea2b8888a4
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Update copyright years
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2022-06-09 00:12:01 +01:00 |
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Luke Wren
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ae2784d0ea
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PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.
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2022-06-03 17:09:43 +01:00 |
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Luke Wren
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e0a9fb7312
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Add option to hardwire PMP regions, or reduce their granularity
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2022-06-03 01:19:03 +01:00 |
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Luke Wren
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d62861159f
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First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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5466c8131e
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Sketch in PMP implementation
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2022-05-23 18:06:23 +01:00 |
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Luke Wren
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5f4127948d
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Add a parameter to control register file reset, instead of the weird ifdef tree
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2022-05-23 13:29:44 +01:00 |
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Luke Wren
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43e0b1d16a
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Implement Zbkb (untested)
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2022-05-06 17:36:25 +01:00 |
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Luke Wren
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2c8f3974d0
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Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
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2022-04-09 13:49:16 +01:00 |
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Luke Wren
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be80bd4c18
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Radical opinion, we should have good performance by default, not bad
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2022-04-02 17:53:22 +01:00 |
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Luke Wren
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7dc5046505
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Perf option for dedicated branch comparator
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2022-04-02 11:40:47 +01:00 |
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Luke Wren
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b0b8703ea4
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Support up to 128 IRQs
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2022-03-13 09:27:43 +00:00 |
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Luke Wren
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bf15b6c49f
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Fix forward reference to net
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2022-01-18 23:02:39 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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c5e85dea4c
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Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
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Luke Wren
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c8afb4ac33
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Add option for fast high-half multiplies
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2021-11-29 18:48:02 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
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Luke Wren
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63d661af63
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Start hacking in debug support to the core -- seems to work as well as before adding debug!
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2021-07-10 18:53:48 +01:00 |
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Luke Wren
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3312ea7022
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Add draft UART DTM
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2021-07-08 17:57:46 +01:00 |
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Luke Wren
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6a38fc33a6
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Allow MHARTID to be configured at instantiation
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2021-07-07 16:08:08 +01:00 |
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Luke Wren
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5f8d217395
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Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
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2021-05-31 17:54:12 +01:00 |
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Luke Wren
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12851d3742
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Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
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2021-05-30 19:52:46 +01:00 |
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Luke Wren
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565b76672a
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Make MVENDORID/MARCHID/MIMPID configurable
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2021-05-30 18:42:43 +01:00 |
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Luke Wren
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844fa8f97f
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Rename hazard5 -> hazard3
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2021-05-21 03:46:29 +01:00 |