5aee830ac0
Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
...
(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
a861a110c1
Update to the latest riscv-arch-test. This uses the new test
...
framework -- scripts are a little janky for now.
Note there is one test failure (cebreak-01) -- analysis shows
this is due to the reference vector expecting mtval to be set
informatively, whereas our implementation (legally) ties it
to zero. Non-mtval-related signature for that test is correct
so I'm saying this is fine.
2023-03-31 01:39:48 +01:00
18d3b03cc8
Fix rm of build directory in tb_cxxrtl/Makefile
2023-03-30 22:43:48 +01:00
97121afa91
Extend testbench to allow dumping/replaying JTAG to text file.
...
This allows debugging of tests that behave differently when VCD dumping
is enabled, due to the difference in execution speed.
(A couple of the SMP debug tests fail intermittently.)
2023-03-27 00:17:11 +01:00
c41fe0609b
Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
...
Fix a couple of minor test script issues.
2023-03-26 23:00:18 +01:00
94bd965e4e
Add script for running SMP debug tests
2023-03-24 18:45:11 +00:00
97509f548a
tb_cxxrtl Makefile: better support for building multiple tb configurations
2023-03-24 18:44:37 +00:00
cbb490da6a
Bump riscv-tests for hazard3 SMP debug test config changes
2023-03-24 18:11:08 +00:00
0dd6be181d
Fix up HwbpManual test in riscv-tests fork, and update debug test list
2023-03-24 00:28:02 +00:00
532e27dbc9
Bump riscv-tests for new debug and ISA tests. (Rebase of Hazard3 patches)
2023-03-23 23:32:28 +00:00
56586def8d
List Zcb/Zcmp in docs, and rebuild PDF
2023-03-22 03:04:16 +00:00
95faab6f2c
Add zcmp_irq_kill test
2023-03-22 02:44:03 +00:00
e98d7b41ea
Hook up power control signals on dual-core tb
2023-03-22 00:34:19 +00:00
8f461b63b4
Fix mvsa01/mva01s in rvcpp
2023-03-21 21:54:04 +00:00
410d002372
First pass at adding Zcmp to rvcpp
2023-03-21 21:28:49 +00:00
8e7e8f4008
Extend rvcpp ISA sim to cover RVC. Passes RV32IC compliance.
2023-03-21 19:38:46 +00:00
f702fe5352
Add test covering all pop instructions
2023-03-20 18:26:29 +00:00
d2adc6aad7
Add tests for mva01s/mvsa01
2023-03-20 16:05:07 +00:00
142b3a81ff
Add spike-extracted output to zcmp_push
2023-03-20 15:37:38 +00:00
ee6e03e0e6
Add beginnings of Spike-able zcmp_push test
2023-03-20 14:26:53 +00:00
3b2ddee06b
Fix push/pop frame format, fix source regnums for mvsa01/mva01s
2023-03-20 02:35:18 +00:00
7702c44288
Handle timeout in runtests
2023-03-20 01:32:16 +00:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
78d937e5c8
Yeet Zcb into core
2023-03-16 18:48:15 +00:00
a247c5cfc1
Bump riscv-tests fork: fix breakpoint test not setting tcontrol.mte when it is implemented.
2023-03-16 17:50:52 +00:00
7fbdb69328
Allow reconnecting to the testbench JTAG socket
2022-12-17 11:58:14 +00:00
8e7ffb040c
Comment typo
2022-12-17 11:39:47 +00:00
dff278ea05
Increase DTM idle cycle hint to 8 cycles -- see #6
2022-10-19 21:11:18 +01:00
0b18fae32e
Fix swapped MHARTID/MCONFIGPTR values in tb configs
2022-10-08 08:42:50 +01:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
a18c3018e1
Bump riscv-formal to head of hazard3 branch, not sure what happened there
2022-10-07 01:35:10 +01:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
da4097ecd8
Delay pwrup_req->pwrup_ack in tb
2022-08-29 14:55:11 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
bf38d93d33
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
2022-08-28 14:15:20 +01:00
a79c857d82
Bump riscv-tests: enable hardware instruction breakpoints in hardware tests
2022-08-27 17:05:02 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
6e2076268c
Update CSR readability/writability tests for new CSRs
2022-08-22 08:50:57 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
8b630d2ac6
Whoops I needed that constant
2022-08-10 01:00:47 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
5894ddf15c
Fix outdated expected output in irq_set_all_with_pri test
2022-08-08 18:44:58 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
2e3d69e98f
Forgot to add expected output for preemption test
2022-08-07 22:08:50 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
9787c604ad
Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
2022-07-30 17:31:53 +01:00
Luke Wren
Scott Shawcroft